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<P class=3Dmediumtext><SPAN class=3Dmaintitle>flat =
assembler</SPAN><BR>Documentation=20
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<DIV class=3Dcontainer>
<P><B><SPAN class=3Dlargetext>flat assembler 1.70</SPAN><BR><SPAN=20
class=3Dmediumtext>Programmer's Manual</SPAN><BR></B></P>
<P><B><SPAN class=3Dlargetext>Table of Contents</SPAN><BR><BR><SPAN=20
class=3Dmediumtext>Chapter 1 - Introduction</SPAN><BR><BR><A=20
style=3D"PADDING-LEFT: 20pt" class=3Dmediumtext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.1">1.1 =
Compiler=20
overview</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.1.1">1.1.1 =
System=20
requirements</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.1.2">1.1.2 =
Executing=20
compiler from command line</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.1.3">1.1.3 =
Compiler=20
messages</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.1.4">1.1.4 =
Output=20
formats</A><BR><BR><A style=3D"PADDING-LEFT: 20pt" class=3Dmediumtext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2">1.2 =
Assembly=20
syntax</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.1">1.2.1 =
Instruction=20
syntax</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.2">1.2.2 =
Data=20
definitions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.3">1.2.3 =
Constants=20
and labels</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.4">1.2.4 =
Numerical=20
expressions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.5">1.2.5 =
Jumps and=20
calls</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.6">1.2.6 =
Size=20
settings</A><BR><BR><SPAN class=3Dmediumtext>Chapter 2 - Instruction=20
Set</SPAN><BR><BR><A style=3D"PADDING-LEFT: 20pt" class=3Dmediumtext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1">2.1 The =
x86=20
architecture instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.1">2.1.1 =
Data=20
movement instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.2">2.1.2 =
Type=20
conversion instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.3">2.1.3 =
Binary=20
arithmetic instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.4">2.1.4 =
Decimal=20
arithmetic instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.5">2.1.5 =
Logical=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.6">2.1.6 =
Control=20
transfer instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.7">2.1.7 =
I/O=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.8">2.1.8 =
Strings=20
operations</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.9">2.1.9 =
Flag control=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.10">2.1.10=
=20
Conditional operations</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.11">2.1.11=
=20
Miscellaneous instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.12">2.1.12=
 System=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.13">2.1.13=
 FPU=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.14">2.1.14=
 MMX=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.15">2.1.15=
 SSE=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.16">2.1.16=
 SSE2=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.17">2.1.17=
 SSE3=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.18">2.1.18=
 AMD 3DNow!=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.19">2.1.19=
 The x86-64=20
long mode instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.20">2.1.20=
 SSE4=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.21">2.1.21=
 AVX=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.22">2.1.22=
 AVX2=20
instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.23">2.1.23=
 Auxiliary=20
sets of computational instructions</A><BR><A style=3D"PADDING-LEFT: =
40pt"=20
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.24">2.1.24=
 Other=20
extensions of instruction set</A><BR><BR><A style=3D"PADDING-LEFT: 20pt" =

class=3Dmediumtext =
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2">2.2=20
Control directives</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.1">2.2.1 =
Numerical=20
constants</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.2">2.2.2 =
Conditional=20
assembly</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.3">2.2.3 =
Repeating=20
blocks of instructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.4">2.2.4 =
Addressing=20
spaces</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.5">2.2.5 =
Other=20
directives</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.6">2.2.6 =
Multiple=20
passes</A><BR><BR><A style=3D"PADDING-LEFT: 20pt" class=3Dmediumtext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3">2.3 =
Preprocessor=20
directives</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.1">2.3.1 =
Including=20
source files</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.2">2.3.2 =
Symbolic=20
constants</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.3">2.3.3=20
Macroinstructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.4">2.3.4=20
Structures</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.5">2.3.5 =
Repeating=20
macroinstructions</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.6">2.3.6 =
Conditional=20
preprocessing</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.7">2.3.7 =
Order of=20
processing</A><BR><BR><A style=3D"PADDING-LEFT: 20pt" class=3Dmediumtext =

href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4">2.4 =
Formatter=20
directives</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4.1">2.4.1 =
MZ=20
executable</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4.2">2.4.2 =
Portable=20
Executable</A><BR><A style=3D"PADDING-LEFT: 40pt" class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4.3">2.4.3 =
Common=20
Object File Format</A><BR><A style=3D"PADDING-LEFT: 40pt" =
class=3Dsmalltext=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4.4">2.4.4 =
Executable=20
and Linkable Format</A><BR></B></P>
<P><B><SPAN class=3Dmediumtext>Chapter 1</SPAN><BR><SPAN=20
class=3Dlargetext>Introduction</SPAN><BR></B></P>
<P class=3Dsmalltext>This chapter contains all the most important =
information you=20
need to begin using the flat assembler. If you are experienced assembly =
language=20
programmer, you should read at least this chapter before using this =
compiler.=20
</P>
<P><B><A class=3Dmediumtext name=3D1.1>1.1 Compiler overview</A> =
</B></P>
<P class=3Dsmalltext>Flat assembler is a fast assembly language compiler =
for the=20
x86 architecture processors, which does multiple passes to optimize the =
size of=20
generated machine code. It is self-compilable and versions for different =

operating systems are provided. All the versions are designed to be used =
from=20
the system command line and they should not differ in behavior. </P>
<P><B><A class=3Dsmalltext name=3D1.1.1>1.1.1 System requirements</A> =
</B></P>
<P class=3Dsmalltext>All versions require the x86 architecture 32-bit =
processor=20
(at least 80386), although they can produce programs for the x86 =
architecture=20
16-bit processors, too. DOS version requires an OS compatible with MS =
DOS 2.0=20
and either true real mode environment or DPMI. Windows version requires =
a Win32=20
console compatible with 3.1 version. </P>
<P><B><A class=3Dsmalltext name=3D1.1.2>1.1.2 Executing compiler from =
command=20
line</A> </B></P>
<P class=3Dsmalltext>To execute flat assembler from the command line you =
need to=20
provide two parameters - first should be name of source file, second =
should be=20
name of destination file. If no second parameter is given, the name for =
output=20
file will be guessed automatically. After displaying short information =
about the=20
program name and version, compiler will read the data from source file =
and=20
compile it. When the compilation is successful, compiler will write the=20
generated code to the destination file and display the summary of =
compilation=20
process; otherwise it will display the information about error that =
occurred.=20
</P>
<P class=3Dsmalltext>In the command line you can also include <SPAN=20
class=3Dsmallcode>-m</SPAN> option followed by a number, which specifies =
how many=20
kilobytes of memory flat assembler should maximally use. In case of DOS =
version=20
this options limits only the usage of extended memory. The <SPAN=20
class=3Dsmallcode>-p</SPAN> option followed by a number can be used to =
specify the=20
limit for number of passes the assembler performs. If code cannot be =
generated=20
within specified amount of passes, the assembly will be terminated with =
an error=20
message. The maximum value of this setting is 65536, while the default =
limit,=20
used when no such option is included in command line, is 100. </P>
<P class=3Dsmalltext>The source file should be a text file, and can be =
created in=20
any text editor. Line breaks are accepted in both DOS and Unix =
standards,=20
tabulators are treated as spaces. </P>
<P class=3Dsmalltext>There are no command line options that would affect =
the=20
output of compiler, flat assembler requires only the source code to =
include the=20
information it really needs. For example, to specify output format you =
specify=20
it by using the <SPAN class=3Dsmallcode>format</SPAN> directive at the =
beginning=20
of source. </P>
<P><B><A class=3Dsmalltext name=3D1.1.3>1.1.3 Compiler messages</A> =
</B></P>
<P class=3Dsmalltext>As it is stated above, after the successful =
compilation, the=20
compiler displays the compilation summary. It includes the information =
of how=20
many passes was done, how much time it took, and how many bytes were =
written=20
into the destination file. The following is an example of the =
compilation=20
summary: </P><PRE class=3Dsmallcode>flat assembler  version 1.70 (16384 =
kilobytes memory)
38 passes, 5.3 seconds, 77824 bytes.
</PRE>
<P class=3Dsmalltext>In case of error during the compilation process, =
the program=20
will display an error message. For example, when compiler can't find the =
input=20
file, it will display the following message: </P><PRE =
class=3Dsmallcode>flat assembler  version 1.70 (16384 kilobytes memory)
error: source file not found.
</PRE>
<P class=3Dsmalltext>If the error is connected with a specific part of =
source=20
code, the source line that caused the error will be also displayed. Also =

placement of this line in the source is given to help you finding this =
error,=20
for example: </P><PRE class=3Dsmallcode>flat assembler  version 1.70 =
(16384 kilobytes memory)
example.asm [3]:
        mob     ax,1
error: illegal instruction.
</PRE>
<P class=3Dsmalltext>It means that in the third line of the <SPAN=20
class=3Dsmallcode>example.asm</SPAN> file compiler has encountered an =
unrecognized=20
instruction. When the line that caused error contains a =
macroinstruction, also=20
the line in macroinstruction definition that generated the erroneous =
instruction=20
is displayed: </P><PRE class=3Dsmallcode>flat assembler  version 1.70 =
(16384 kilobytes memory)
example.asm [6]:
        stoschar 7
example.asm [3] stoschar [1]:
        mob     al,char
error: illegal instruction.
</PRE>
<P class=3Dsmalltext>It means that the macroinstruction in the sixth =
line of the=20
<SPAN class=3Dsmallcode>example.asm</SPAN> file generated an =
unrecognized=20
instruction with the first line of its definition. </P>
<P><B><A class=3Dsmalltext name=3D1.1.4>1.1.4 Output formats</A> =
</B></P>
<P class=3Dsmalltext>By default, when there is no <SPAN=20
class=3Dsmallcode>format</SPAN> directive in source file, flat assembler =
simply=20
puts generated instruction codes into output, creating this way flat =
binary=20
file. By default it generates 16-bit code, but you can always turn it =
into the=20
16-bit or 32-bit mode by using <SPAN class=3Dsmallcode>use16</SPAN> or =
<SPAN=20
class=3Dsmallcode>use32</SPAN> directive. Some of the output formats =
switch into=20
32-bit mode, when selected - more information about formats which you =
can choose=20
can be found in <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4">2.4</A>. =
</P>
<P class=3Dsmalltext>All output code is always in the order in which it =
was=20
entered into the source file. </P>
<P><B><A class=3Dmediumtext name=3D1.2>1.2 Assembly syntax</A> </B></P>
<P class=3Dsmalltext>The information provided below is intended mainly =
for the=20
assembler programmers that have been using some other assembly compilers =
before.=20
If you are beginner, you should look for the assembly programming =
tutorials.=20
</P>
<P class=3Dsmalltext>Flat assembler by default uses the Intel syntax for =
the=20
assembly instructions, although you can customize it using the =
preprocessor=20
capabilities (macroinstructions and symbolic constants). It also has its =
own set=20
of the directives - the instructions for compiler. </P>
<P class=3Dsmalltext>All symbols defined inside the sources are =
case-sensitive.=20
</P>
<P><B><A class=3Dsmalltext name=3D1.2.1>1.2.1 Instruction syntax</A> =
</B></P>
<P class=3Dsmalltext>Instructions in assembly language are separated by =
line=20
breaks, and one instruction is expected to fill the one line of text. If =
a line=20
contains a semicolon, except for the semicolons inside the quoted =
strings, the=20
rest of this line is the comment and compiler ignores it. If a line ends =
with=20
<SPAN class=3Dsmallcode>\</SPAN> character (eventually the semicolon and =
comment=20
may follow it), the next line is attached at this point. </P>
<P class=3Dsmalltext>Each line in source is the sequence of items, which =
may be=20
one of the three types. One type are the symbol characters, which are =
the=20
special characters that are individual items even when are not spaced =
from the=20
other ones. Any of the <SPAN=20
class=3Dsmallcode>+-/*=3D&lt;&gt;()[]{}:,|&amp;~#`</SPAN> is the symbol =
character.=20
The sequence of other characters, separated from other items with either =
blank=20
spaces or symbol characters, is a symbol. If the first character of =
symbol is=20
either a single or double quote, it integrates any sequence of =
characters=20
following it, even the special ones, into a quoted string, which should =
end with=20
the same character, with which it began (the single or double quote) - =
however=20
if there are two such characters in a row (without any other character =
between=20
them), they are integrated into quoted string as just one of them and =
the quoted=20
string continues then. The symbols other than symbol characters and =
quoted=20
strings can be used as names, so are also called the name symbols. </P>
<P class=3Dsmalltext>Every instruction consists of the mnemonic and the =
various=20
number of operands, separated with commas. The operand can be register,=20
immediate value or a data addressed in memory, it can also be preceded =
by size=20
operator to define or override its size (table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.1">1.1</A>)=
. Names of=20
available registers you can find in table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.2">1.2</A>,=
 their=20
sizes cannot be overridden. Immediate value can be specified by any =
numerical=20
expression. </P>
<P class=3Dsmalltext>When operand is a data in memory, the address of =
that data=20
(also any numerical expression, but it may contain registers) should be =
enclosed=20
in square brackets or preceded by <SPAN class=3Dsmallcode>ptr</SPAN> =
operator. For=20
example instruction <SPAN class=3Dsmallcode>mov eax,3</SPAN> will put =
the=20
immediate value 3 into the EAX register, instruction <SPAN =
class=3Dsmallcode>mov=20
eax,[7]</SPAN> will put the 32-bit value from the address 7 into EAX and =
the=20
instruction <SPAN class=3Dsmallcode>mov byte [7],3</SPAN> will put the =
immediate=20
value 3 into the byte at address 7, it can also be written as <SPAN=20
class=3Dsmallcode>mov byte ptr 7,3</SPAN>. To specify which segment =
register=20
should be used for addressing, segment register name followed by a colon =
should=20
be put just before the address value (inside the square brackets or =
after the=20
<SPAN class=3Dsmallcode>ptr</SPAN> operator). </P>
<P class=3Dsmalltext><B><A name=3D_1.1>Table 1.1 Size operators</A></B> =
</P>
<TABLE style=3D"WIDTH: 150px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Operator</TH>
    <TH>Bits</TH>
    <TH>Bytes</TH></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>byte</SPAN></TD>
    <TD>8</TD>
    <TD>1</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>word</SPAN></TD>
    <TD>16</TD>
    <TD>2</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>dword</SPAN></TD>
    <TD>32</TD>
    <TD>4</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>fword</SPAN></TD>
    <TD>48</TD>
    <TD>6</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>pword</SPAN></TD>
    <TD>48</TD>
    <TD>6</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>qword</SPAN></TD>
    <TD>64</TD>
    <TD>8</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>tbyte</SPAN></TD>
    <TD>80</TD>
    <TD>10</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>tword</SPAN></TD>
    <TD>80</TD>
    <TD>10</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>dqword</SPAN></TD>
    <TD>128</TD>
    <TD>16</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>xword</SPAN></TD>
    <TD>128</TD>
    <TD>16</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>qqword</SPAN></TD>
    <TD>256</TD>
    <TD>32</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>yword</SPAN></TD>
    <TD>256</TD>
    <TD>32</TD></TR></TBODY></TABLE>
<P class=3Dsmalltext><B><A name=3D_1.2>Table 1.2 Registers</A></B> </P>
<TABLE style=3D"WIDTH: 430px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH style=3D"WIDTH: 70px">Type</TH>
    <TH style=3D"WIDTH: 40px">Bits</TH>
    <TH></TH></TR>
  <TR>
    <TD rowSpan=3D3>General</TD>
    <TD>8</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>al</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cl</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dl</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>bl</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ah</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ch</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dh</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>bh</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>16</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ax</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>bx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>sp</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>bp</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>si</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>di</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>32</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>eax</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ecx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>edx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ebx</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>esp</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ebp</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>esi</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>edi</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>Segment</TD>
    <TD>16</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>es</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cs</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ss</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ds</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>fs</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>gs</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        =
class=3Dsmallcode>&nbsp;</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>Control</TD>
    <TD>32</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cr0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cr2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cr3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>cr4</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        =
class=3Dsmallcode>&nbsp;</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>Debug</TD>
    <TD>32</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dr0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dr1</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dr2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dr3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>&nbsp;</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>dr6</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>dr7</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>FPU</TD>
    <TD>80</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st1</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st4</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st5</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>st6</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>st7</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>MMX</TD>
    <TD>64</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm1</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm4</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm5</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>mm6</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        class=3Dsmallcode>mm7</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>SSE</TD>
    <TD>128</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm1</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm4</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm5</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>xmm6</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        =
class=3Dsmallcode>xmm7</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>AVX</TD>
    <TD>256</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm0</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm1</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm2</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm3</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm4</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm5</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN =
class=3Dsmallcode>ymm6</SPAN></TD>
          <TD style=3D"WIDTH: 12.5%"><SPAN=20
        =
class=3Dsmallcode>ymm7</SPAN></TD></TR></TBODY></TABLE></TD></TR></TBODY>=
</TABLE>
<P><B><A class=3Dsmalltext name=3D1.2.2>1.2.2 Data definitions</A> =
</B></P>
<P class=3Dsmalltext>To define data or reserve a space for it, use one =
of the=20
directives listed in table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.3">1.3</A>.=
 The data=20
definition directive should be followed by one or more of numerical =
expressions,=20
separated with commas. These expressions define the values for data =
cells of=20
size depending on which directive is used. For example <SPAN =
class=3Dsmallcode>db=20
1,2,3</SPAN> will define the three bytes of values 1, 2 and 3 =
respectively. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>db</SPAN> and <SPAN=20
class=3Dsmallcode>du</SPAN> directives also accept the quoted string =
values of any=20
length, which will be converted into chain of bytes when <SPAN=20
class=3Dsmallcode>db</SPAN> is used and into chain of words with zeroed =
high byte=20
when <SPAN class=3Dsmallcode>du</SPAN> is used. For example <SPAN=20
class=3Dsmallcode>db 'abc'</SPAN> will define the three bytes of values =
61, 62 and=20
63. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>dp</SPAN> directive and =
its synonym=20
<SPAN class=3Dsmallcode>df</SPAN> accept the values consisting of two =
numerical=20
expressions separated with colon, the first value will become the high =
word and=20
the second value will become the low double word of the far pointer =
value. Also=20
<SPAN class=3Dsmallcode>dd</SPAN> accepts such pointers consisting of =
two word=20
values separated with colon, and <SPAN class=3Dsmallcode>dt</SPAN> =
accepts the=20
word and quad word value separated with colon, the quad word is stored =
first.=20
The <SPAN class=3Dsmallcode>dt</SPAN> directive with single expression =
as=20
parameter accepts only floating point values and creates data in FPU =
double=20
extended precision format. </P>
<P class=3Dsmalltext>Any of the above directive allows the usage of =
special <SPAN=20
class=3Dsmallcode>dup</SPAN> operator to make multiple copies of given =
values. The=20
count of duplicates should precede this operator and the value to =
duplicate=20
should follow - it can even be the chain of values separated with =
commas, but=20
such set of values needs to be enclosed with parenthesis, like <SPAN=20
class=3Dsmallcode>db&nbsp;5&nbsp;dup&nbsp;(1,2)</SPAN>, which defines =
five copies=20
of the given two byte sequence. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>file</SPAN> is a =
special directive=20
and its syntax is different. This directive includes a chain of bytes =
from file=20
and it should be followed by the quoted file name, then optionally =
numerical=20
expression specifying offset in file preceded by the colon, then - also=20
optionally - comma and numerical expression specifying count of bytes to =
include=20
(if no count is specified, all data up to the end of file is included). =
For=20
example <SPAN class=3Dsmallcode>file&nbsp;'data.bin'</SPAN> will include =
the whole=20
file as binary data and <SPAN =
class=3Dsmallcode>file&nbsp;'data.bin':10h,4</SPAN>=20
will include only four bytes starting at offset 10h. </P>
<P class=3Dsmalltext>The data reservation directive should be followed =
by only one=20
numerical expression, and this value defines how many cells of the =
specified=20
size should be reserved. All data definition directives also accept the =
<SPAN=20
class=3Dsmallcode>?</SPAN> value, which means that this cell should not =
be=20
initialized to any value and the effect is the same as by using the data =

reservation directive. The uninitialized data may not be included in the =
output=20
file, so its values should be always considered unknown. </P>
<P class=3Dsmalltext><B><A name=3D_1.3>Table 1.3 Data directives</A></B> =
</P>
<TABLE style=3D"WIDTH: 150px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Size (bytes)</TH>
    <TH>Define data</TH>
    <TH>Reserve data</TH></TR>
  <TR>
    <TD>1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>db</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>file</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD><SPAN class=3Dsmallcode>rb</SPAN></TD></TR>
  <TR>
    <TD>2</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>dw</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>du</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD><SPAN class=3Dsmallcode>rw</SPAN></TD></TR>
  <TR>
    <TD>4</TD>
    <TD><SPAN class=3Dsmallcode>dd</SPAN></TD>
    <TD><SPAN class=3Dsmallcode>rd</SPAN></TD></TR>
  <TR>
    <TD>6</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>dp</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>df</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>rp</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>rf</SPAN></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>8</TD>
    <TD><SPAN class=3Dsmallcode>dq</SPAN></TD>
    <TD><SPAN class=3Dsmallcode>rq</SPAN></TD></TR>
  <TR>
    <TD>10</TD>
    <TD><SPAN class=3Dsmallcode>dt</SPAN></TD>
    <TD><SPAN class=3Dsmallcode>rt</SPAN></TD></TR></TBODY></TABLE>
<P><B><A class=3Dsmalltext name=3D1.2.3>1.2.3 Constants and labels</A> =
</B></P>
<P class=3Dsmalltext>In the numerical expressions you can also use =
constants or=20
labels instead of numbers. To define the constant or label you should =
use the=20
specific directives. Each label can be defined only once and it is =
accessible=20
from the any place of source (even before it was defined). Constant can =
be=20
redefined many times, but in this case it is accessible only after it =
was=20
defined, and is always equal to the value from last definition before =
the place=20
where it's used. When a constant is defined only once in source, it is - =
like=20
the label - accessible from anywhere. </P>
<P class=3Dsmalltext>The definition of constant consists of name of the =
constant=20
followed by the <SPAN class=3Dsmallcode>=3D</SPAN> character and =
numerical=20
expression, which after calculation will become the value of constant. =
This=20
value is always calculated at the time the constant is defined. For =
example you=20
can define <SPAN class=3Dsmallcode>count</SPAN> constant by using the =
directive=20
<SPAN class=3Dsmallcode>count =3D 17</SPAN> and then use it in the =
assembly=20
instructions, like <SPAN class=3Dsmallcode>mov cx,count</SPAN> - which =
will become=20
<SPAN class=3Dsmallcode>mov cx,17</SPAN> during the compilation process. =
</P>
<P class=3Dsmalltext>There are different ways to define labels. The =
simplest is to=20
follow the name of label by the colon, this directive can even be =
followed by=20
the other instruction in the same line. It defines the label whose value =
is=20
equal to offset of the point where it's defined. This method is usually =
used to=20
label the places in code. The other way is to follow the name of label =
(without=20
a colon) by some data directive. It defines the label with value equal =
to offset=20
of the beginning of defined data, and remembered as a label for data =
with cell=20
size as specified for that data directive in table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.3">1.3</A>.=
 </P>
<P class=3Dsmalltext>The label can be treated as constant of value equal =
to offset=20
of labeled code or data. For example when you define data using the =
labeled=20
directive <SPAN class=3Dsmallcode>char db 224</SPAN>, to put the offset =
of this=20
data into BX register you should use <SPAN class=3Dsmallcode>mov =
bx,char</SPAN>=20
instruction, and to put the value of byte addressed by <SPAN=20
class=3Dsmallcode>char</SPAN> label to DL register, you should use <SPAN =

class=3Dsmallcode>mov dl,[char]</SPAN> (or <SPAN class=3Dsmallcode>mov =
dl,ptr=20
char</SPAN>). But when you try to assemble <SPAN class=3Dsmallcode>mov=20
ax,[char]</SPAN>, it will cause an error, because fasm compares the =
sizes of=20
operands, which should be equal. You can force assembling that =
instruction by=20
using size override: <SPAN class=3Dsmallcode>mov ax,word [char]</SPAN>, =
but=20
remember that this instruction will read the two bytes beginning at =
<SPAN=20
class=3Dsmallcode>char</SPAN> address, while it was defined as a one =
byte. </P>
<P class=3Dsmalltext>The last and the most flexible way to define labels =
is to use=20
<SPAN class=3Dsmallcode>label</SPAN> directive. This directive should be =
followed=20
by the name of label, then optionally size operator (it can be preceded =
by a=20
colon) and then - also optionally <SPAN class=3Dsmallcode>at</SPAN> =
operator and=20
the numerical expression defining the address at which this label should =
be=20
defined. For example <SPAN class=3Dsmallcode>label wchar word at =
char</SPAN> will=20
define a new label for the 16-bit data at the address of <SPAN=20
class=3Dsmallcode>char</SPAN>. Now the instruction <SPAN =
class=3Dsmallcode>mov=20
ax,[wchar]</SPAN> will be after compilation the same as <SPAN=20
class=3Dsmallcode>mov ax,word [char]</SPAN>. If no address is specified, =
<SPAN=20
class=3Dsmallcode>label</SPAN> directive defines the label at current =
offset. Thus=20
<SPAN class=3Dsmallcode>mov [wchar],57568</SPAN> will copy two bytes =
while <SPAN=20
class=3Dsmallcode>mov [char],224</SPAN> will copy one byte to the same =
address.=20
</P>
<P class=3Dsmalltext>The label whose name begins with dot is treated as =
local=20
label, and its name is attached to the name of last global label (with =
name=20
beginning with anything but dot) to make the full name of this label. So =
you can=20
use the short name (beginning with dot) of this label anywhere before =
the next=20
global label is defined, and in the other places you have to use the =
full name.=20
Label beginning with two dots are the exception - they are like global, =
but they=20
don't become the new prefix for local labels. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>@@</SPAN> name means =
anonymous=20
label, you can have defined many of them in the source. Symbol <SPAN=20
class=3Dsmallcode>@b</SPAN> (or equivalent <SPAN =
class=3Dsmallcode>@r</SPAN>)=20
references the nearest preceding anonymous label, symbol <SPAN=20
class=3Dsmallcode>@f</SPAN> references the nearest following anonymous =
label.=20
These special symbol are case-insensitive. </P>
<P><B><A class=3Dsmalltext name=3D1.2.4>1.2.4 Numerical expressions</A> =
</B></P>
<P class=3Dsmalltext>In the above examples all the numerical expressions =
were the=20
simple numbers, constants or labels. But they can be more complex, by =
using the=20
arithmetical or logical operators for calculations at compile time. All =
these=20
operators with their priority values are listed in table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.4">1.4</A>.=
 The=20
operations with higher priority value will be calculated first, you can =
of=20
course change this behavior by putting some parts of expression into=20
parenthesis. The <SPAN class=3Dsmallcode>+</SPAN>, <SPAN =
class=3Dsmallcode>-</SPAN>,=20
<SPAN class=3Dsmallcode>*</SPAN> and <SPAN class=3Dsmallcode>/</SPAN> =
are standard=20
arithmetical operations, <SPAN class=3Dsmallcode>mod</SPAN> calculates =
the=20
remainder from division. The <SPAN class=3Dsmallcode>and</SPAN>, <SPAN=20
class=3Dsmallcode>or</SPAN>, <SPAN class=3Dsmallcode>xor</SPAN>, <SPAN=20
class=3Dsmallcode>shl</SPAN>, <SPAN class=3Dsmallcode>shr</SPAN> and =
<SPAN=20
class=3Dsmallcode>not</SPAN> perform the same logical operations as =
assembly=20
instructions of those names. The <SPAN class=3Dsmallcode>rva</SPAN> and =
<SPAN=20
class=3Dsmallcode>plt</SPAN> are special unary operators that perform =
conversions=20
between different kinds of addresses, they can be used only with few of =
the=20
output formats and their meaning may vary (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4">2.4</A>).=
 </P>
<P class=3Dsmalltext>The artithmetical and logical calculations are =
usually=20
processed as if they operated on infinite precision 2-adic numbers, and=20
assembler signalizes an overflow error if because of its limitations it =
is not=20
table to perform the required calculation, or if the result is too large =
number=20
to fit in either signed or unsigned range for the destination unit size. =
However=20
<SPAN class=3Dsmallcode>not</SPAN>, <SPAN class=3Dsmallcode>xor</SPAN> =
and <SPAN=20
class=3Dsmallcode>shr</SPAN> operators are exceptions from this rule - =
if the=20
value specified by numerical expression has to fit in a unit of =
specified size,=20
and the arguments for operation fit into that size, the operation will =
be=20
performed with precision limited to that size. </P>
<P class=3Dsmalltext>The numbers in the expression are by default =
treated as a=20
decimal, binary numbers should have the <SPAN class=3Dsmallcode>b</SPAN> =
letter=20
attached at the end, octal number should end with <SPAN =
class=3Dsmallcode>o</SPAN>=20
letter, hexadecimal numbers should begin with <SPAN =
class=3Dsmallcode>0x</SPAN>=20
characters (like in C language) or with the <SPAN =
class=3Dsmallcode>$</SPAN>=20
character (like in Pascal language) or they should end with <SPAN=20
class=3Dsmallcode>h</SPAN> letter. Also quoted string, when encountered =
in=20
expression, will be converted into number - the first character will =
become the=20
least significant byte of number. </P>
<P class=3Dsmalltext>The numerical expression used as an address value =
can also=20
contain any of general registers used for addressing, they can be added =
and=20
multiplied by appropriate values, as it is allowed for the x86 =
architecture=20
instructions. The numerical calculations inside address definition by =
default=20
operate with target size assumed to be the same as the current bitness =
of code,=20
even if generated instruction encoding will use a different address =
size. </P>
<P class=3Dsmalltext>There are also some special symbols that can be =
used inside=20
the numerical expression. First is <SPAN class=3Dsmallcode>$</SPAN>, =
which is=20
always equal to the value of current offset, while <SPAN=20
class=3Dsmallcode>$$</SPAN> is equal to base address of current =
addressing space.=20
The other one is <SPAN class=3Dsmallcode>%</SPAN>, which is the number =
of current=20
repeat in parts of code that are repeated using some special directives =
(see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2">2.2</A>) =
and zero=20
anywhere else. There's also <SPAN class=3Dsmallcode>%t</SPAN> symbol, =
which is=20
always equal to the current time stamp. </P>
<P class=3Dsmalltext>Any numerical expression can also consist of single =
floating=20
point value (flat assembler does not allow any floating point operations =
at=20
compilation time) in the scientific notation, they can end with the =
<SPAN=20
class=3Dsmallcode>f</SPAN> letter to be recognized, otherwise they =
should contain=20
at least one of the <SPAN class=3Dsmallcode>.</SPAN> or <SPAN=20
class=3Dsmallcode>E</SPAN> characters. So <SPAN =
class=3Dsmallcode>1.0</SPAN>, <SPAN=20
class=3Dsmallcode>1E0</SPAN> and <SPAN class=3Dsmallcode>1f</SPAN> =
define the same=20
floating point value, while simple <SPAN class=3Dsmallcode>1</SPAN> =
defines an=20
integer value. </P>
<P class=3Dsmalltext><B><A name=3D_1.4>Table 1.4 Arithmetical and =
logical operators=20
by priority</A></B> </P>
<TABLE style=3D"WIDTH: 200px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Priority</TH>
    <TH>Operators</TH></TR>
  <TR>
    <TD>0</TD>
    <TD><SPAN class=3Dsmallcode>+ -</SPAN></TD></TR>
  <TR>
    <TD>1</TD>
    <TD><SPAN class=3Dsmallcode>* /</SPAN></TD></TR>
  <TR>
    <TD>2</TD>
    <TD><SPAN class=3Dsmallcode>mod</SPAN></TD></TR>
  <TR>
    <TD>3</TD>
    <TD><SPAN class=3Dsmallcode>and or xor</SPAN></TD></TR>
  <TR>
    <TD>4</TD>
    <TD><SPAN class=3Dsmallcode>shl shr</SPAN></TD></TR>
  <TR>
    <TD>5</TD>
    <TD><SPAN class=3Dsmallcode>not</SPAN></TD></TR>
  <TR>
    <TD>6</TD>
    <TD><SPAN class=3Dsmallcode>rva plt</SPAN></TD></TR></TBODY></TABLE>
<P><B><A class=3Dsmalltext name=3D1.2.5>1.2.5 Jumps and calls</A> =
</B></P>
<P class=3Dsmalltext>The operand of any jump or call instruction can be =
preceded=20
not only by the size operator, but also by one of the operators =
specifying type=20
of the jump: <SPAN class=3Dsmallcode>short</SPAN>, <SPAN=20
class=3Dsmallcode>near</SPAN> or <SPAN class=3Dsmallcode>far</SPAN>. For =
example,=20
when assembler is in 16-bit mode, instruction <SPAN=20
class=3Dsmallcode>jmp&nbsp;dword&nbsp;[0]</SPAN> will become the far =
jump and when=20
assembler is in 32-bit mode, it will become the near jump. To force this =

instruction to be treated differently, use the <SPAN=20
class=3Dsmallcode>jmp&nbsp;near&nbsp;dword&nbsp;[0]</SPAN> or <SPAN=20
class=3Dsmallcode>jmp&nbsp;far&nbsp;dword&nbsp;[0]</SPAN> form. </P>
<P class=3Dsmalltext>When operand of near jump is the immediate value, =
assembler=20
will generate the shortest variant of this jump instruction if possible =
(but=20
will not create 32-bit instruction in 16-bit mode nor 16-bit instruction =
in=20
32-bit mode, unless there is a size operator stating it). By specifying =
the jump=20
type you can force it to always generate long variant (for example <SPAN =

class=3Dsmallcode>jmp&nbsp;near&nbsp;0</SPAN>) or to always generate =
short variant=20
and terminate with an error when it's impossible (for example <SPAN=20
class=3Dsmallcode>jmp&nbsp;short&nbsp;0</SPAN>). </P>
<P><B><A class=3Dsmalltext name=3D1.2.6>1.2.6 Size settings</A> </B></P>
<P class=3Dsmalltext>When instruction uses some memory addressing, by =
default the=20
smallest form of instruction is generated by using the short =
displacement if=20
only address value fits in the range. This can be overridden using the =
<SPAN=20
class=3Dsmallcode>word</SPAN> or <SPAN class=3Dsmallcode>dword</SPAN> =
operator=20
before the address inside the square brackets (or after the <SPAN=20
class=3Dsmallcode>ptr</SPAN> operator), which forces the long =
displacement of=20
appropriate size to be made. In case when address is not relative to any =

registers, those operators allow also to choose the appropriate mode of =
absolute=20
addressing. </P>
<P class=3Dsmalltext>Instructions <SPAN class=3Dsmallcode>adc</SPAN>, =
<SPAN=20
class=3Dsmallcode>add</SPAN>, <SPAN class=3Dsmallcode>and</SPAN>, <SPAN=20
class=3Dsmallcode>cmp</SPAN>, <SPAN class=3Dsmallcode>or</SPAN>, <SPAN=20
class=3Dsmallcode>sbb</SPAN>, <SPAN class=3Dsmallcode>sub</SPAN> and =
<SPAN=20
class=3Dsmallcode>xor</SPAN> with first operand being 16-bit or 32-bit =
are by=20
default generated in shortened 8-bit form when the second operand is =
immediate=20
value fitting in the range for signed 8-bit values. It also can be =
overridden by=20
putting the <SPAN class=3Dsmallcode>word</SPAN> or <SPAN=20
class=3Dsmallcode>dword</SPAN> operator before the immediate value. The =
similar=20
rules applies to the <SPAN class=3Dsmallcode>imul</SPAN> instruction =
with the last=20
operand being immediate value. </P>
<P class=3Dsmalltext>Immediate value as an operand for <SPAN=20
class=3Dsmallcode>push</SPAN> instruction without a size operator is by =
default=20
treated as a word value if assembler is in 16-bit mode and as a double =
word=20
value if assembler is in 32-bit mode, shorter 8-bit form of this =
instruction is=20
used if possible, <SPAN class=3Dsmallcode>word</SPAN> or <SPAN=20
class=3Dsmallcode>dword</SPAN> size operator forces the <SPAN=20
class=3Dsmallcode>push</SPAN> instruction to be generated in longer form =
for=20
specified size. <SPAN class=3Dsmallcode>pushw</SPAN> and <SPAN=20
class=3Dsmallcode>pushd</SPAN> mnemonics force assembler to generate =
16-bit or=20
32-bit code without forcing it to use the longer form of instruction. =
</P>
<P><B><SPAN class=3Dmediumtext>Chapter 2</SPAN><BR><SPAN=20
class=3Dlargetext>Instruction set</SPAN><BR></B></P>
<P><B><A class=3Dmediumtext name=3D2.1>2.1 The x86 architecture =
instructions</A>=20
</B></P>
<P class=3Dsmalltext>In this section you can find both the information =
about the=20
syntax and purpose the assembly language instructions. If you need more=20
technical information, look for the Intel Architecture Software =
Developer's=20
Manual. </P>
<P class=3Dsmalltext>Assembly instructions consist of the mnemonic =
(instruction's=20
name) and from zero to three operands. If there are two or more =
operands,=20
usually first is the destination operand and second is the source =
operand. Each=20
operand can be register, memory or immediate value (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2">1.2</A> =
for details=20
about syntax of operands). After the description of each instruction =
there are=20
examples of different combinations of operands, if the instruction has =
any. </P>
<P class=3Dsmalltext>Some instructions act as prefixes and can be =
followed by=20
other instruction in the same line, and there can be more than one =
prefix in a=20
line. Each name of the segment register is also a mnemonic of =
instruction=20
prefix, altough it is recommended to use segment overrides inside the =
square=20
brackets instead of these prefixes. </P>
<P><B><A class=3Dsmalltext name=3D2.1.1>2.1.1 Data movement =
instructions</A>=20
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>mov</SPAN> transfers a =
byte, word or=20
double word from the source operand to the destination operand. It can =
transfer=20
data between general registers, from the general register to memory, or =
from=20
memory to general register, but it cannot move from memory to memory. It =
can=20
also transfer an immediate value to general register or memory, segment =
register=20
to general register or memory, general register or memory to segment =
register,=20
control or debug register to general register and general register to =
control or=20
debug register. The <SPAN class=3Dsmallcode>mov</SPAN> can be assembled =
only if=20
the size of source operand and size of destination operand are the same. =
Below=20
are the examples for each of the allowed combinations: </P><PRE =
class=3Dsmallcode>    mov bx,ax       ; general register to general =
register
    mov [char],al   ; general register to memory
    mov bl,[char]   ; memory to general register
    mov dl,32       ; immediate value to general register
    mov [char],32   ; immediate value to memory
    mov ax,ds       ; segment register to general register
    mov [bx],ds     ; segment register to memory
    mov ds,ax       ; general register to segment register
    mov ds,[bx]     ; memory to segment register
    mov eax,cr0     ; control register to general register
    mov cr3,ebx     ; general register to control register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>xchg</SPAN> swaps the =
contents of two=20
operands. It can swap two byte operands, two word operands or two double =
word=20
operands. Order of operands is not important. The operands may be two =
general=20
registers, or general register with memory. For example: </P><PRE =
class=3Dsmallcode>    xchg ax,bx      ; swap two general registers
    xchg al,[char]  ; swap register with memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>push</SPAN> decrements the =
stack frame=20
pointer (ESP register), then transfers the operand to the top of stack =
indicated=20
by ESP. The operand can be memory, general register, segment register or =

immediate value of word or double word size. If operand is an immediate =
value=20
and no size is specified, it is by default treated as a word value if =
assembler=20
is in 16-bit mode and as a double word value if assembler is in 32-bit =
mode.=20
<SPAN class=3Dsmallcode>pushw</SPAN> and <SPAN =
class=3Dsmallcode>pushd</SPAN>=20
mnemonics are variants of this instruction that store the values of word =
or=20
double word size respectively. If more operands follow in the same line=20
(separated only with spaces, not commas), compiler will assemble chain =
of the=20
<SPAN class=3Dsmallcode>push</SPAN> instructions with these operands. =
The examples=20
are with single operands: </P><PRE class=3Dsmallcode>    push ax         =
; store general register
    push es         ; store segment register
    pushw [bx]      ; store memory
    push 1000h      ; store immediate value
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pusha</SPAN> saves the =
contents of the=20
eight general register on the stack. This instruction has no operands. =
There are=20
two version of this instruction, one 16-bit and one 32-bit, assembler=20
automatically generates the appropriate version for current mode, but it =
can be=20
overridden by using <SPAN class=3Dsmallcode>pushaw</SPAN> or <SPAN=20
class=3Dsmallcode>pushad</SPAN> mnemonic to always get the 16-bit or =
32-bit=20
version. The 16-bit version of this instruction pushes general registers =
on the=20
stack in the following order: AX, CX, DX, BX, the initial value of SP =
before AX=20
was pushed, BP, SI and DI. The 32-bit version pushes equivalent 32-bit =
general=20
registers in the same order. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pop</SPAN> transfers the =
word or double=20
word at the current top of stack to the destination operand, and then =
increments=20
ESP to point to the new top of stack. The operand can be memory, general =

register or segment register. <SPAN class=3Dsmallcode>popw</SPAN> and =
<SPAN=20
class=3Dsmallcode>popd</SPAN> mnemonics are variants of this instruction =
for=20
restoring the values of word or double word size respectively. If more =
operands=20
separated with spaces follow in the same line, compiler will assemble =
chain of=20
the <SPAN class=3Dsmallcode>pop</SPAN> instructions with these operands. =
</P><PRE class=3Dsmallcode>    pop bx          ; restore general =
register
    pop ds          ; restore segment register
    popw [si]       ; restore memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>popa</SPAN> restores the =
registers=20
saved on the stack by <SPAN class=3Dsmallcode>pusha</SPAN> instruction, =
except for=20
the saved value of SP (or ESP), which is ignored. This instruction has =
no=20
operands. To force assembling 16-bit or 32-bit version of this =
instruction use=20
<SPAN class=3Dsmallcode>popaw</SPAN> or <SPAN =
class=3Dsmallcode>popad</SPAN>=20
mnemonic. </P>
<P><B><A class=3Dsmalltext name=3D2.1.2>2.1.2 Type conversion =
instructions</A>=20
</B></P>
<P class=3Dsmalltext>The type conversion instructions convert bytes into =
words,=20
words into double words, and double words into quad words. These =
conversions can=20
be done using the sign extension or zero extension. The sign extension =
fills the=20
extra bits of the larger item with the value of the sign bit of the =
smaller=20
item, the zero extension simply fills them with zeros. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cwd</SPAN> and <SPAN=20
class=3Dsmallcode>cdq</SPAN> double the size of value AX or EAX register =

respectively and store the extra bits into the DX or EDX register. The=20
conversion is done using the sign extension. These instructions have no=20
operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cbw</SPAN> extends the sign =
of the byte=20
in AL throughout AX, and <SPAN class=3Dsmallcode>cwde</SPAN> extends the =
sign of=20
the word in AX throughout EAX. These instructions also have no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movsx</SPAN> converts a =
byte to word or=20
double word and a word to double word using the sign extension. <SPAN=20
class=3Dsmallcode>movzx</SPAN> does the same, but it uses the zero =
extension. The=20
source operand can be general register or memory, while the destination =
operand=20
must be a general register. For example: </P><PRE class=3Dsmallcode>    =
movsx ax,al         ; byte register to word register
    movsx edx,dl        ; byte register to double word register
    movsx eax,ax        ; word register to double word register
    movsx ax,byte [bx]  ; byte memory to word register
    movsx edx,byte [bx] ; byte memory to double word register
    movsx eax,word [bx] ; word memory to double word register
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.3>2.1.3 Binary arithmetic =
instructions</A>=20
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>add</SPAN> replaces the =
destination=20
operand with the sum of the source and destination operands and sets CF =
if=20
overflow has occurred. The operands may be bytes, words or double words. =
The=20
destination operand can be general register or memory, the source =
operand can be=20
general register or immediate value, it can also be memory if the =
destination=20
operand is register. </P><PRE class=3Dsmallcode>    add ax,bx       ; =
add register to register
    add ax,[si]     ; add memory to register
    add [di],al     ; add register to memory
    add al,48       ; add immediate value to register
    add [char],48   ; add immediate value to memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>adc</SPAN> sums the =
operands, adds one=20
if CF is set, and replaces the destination operand with the result. =
Rules for=20
the operands are the same as for the <SPAN class=3Dsmallcode>add</SPAN>=20
instruction. An <SPAN class=3Dsmallcode>add</SPAN> followed by multiple =
<SPAN=20
class=3Dsmallcode>adc</SPAN> instructions can be used to add numbers =
longer than=20
32 bits. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>inc</SPAN> adds one to the =
operand, it=20
does not affect CF. The operand can be general register or memory, and =
the size=20
of the operand can be byte, word or double word. </P><PRE =
class=3Dsmallcode>    inc ax          ; increment register by one
    inc byte [bx]   ; increment memory by one
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>sub</SPAN> subtracts the =
source operand=20
from the destination operand and replaces the destination operand with =
the=20
result. If a borrow is required, the CF is set. Rules for the operands =
are the=20
same as for the <SPAN class=3Dsmallcode>add</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>sbb</SPAN> subtracts the =
source operand=20
from the destination operand, subtracts one if CF is set, and stores the =
result=20
to the destination operand. Rules for the operands are the same as for =
the <SPAN=20
class=3Dsmallcode>add</SPAN> instruction. A <SPAN =
class=3Dsmallcode>sub</SPAN>=20
followed by multiple <SPAN class=3Dsmallcode>sbb</SPAN> instructions may =
be used=20
to subtract numbers longer than 32 bits. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>dec</SPAN> subtracts one =
from the=20
operand, it does not affect CF. Rules for the operand are the same as =
for the=20
<SPAN class=3Dsmallcode>inc</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmp</SPAN> subtracts the =
source operand=20
from the destination operand. It updates the flags as the <SPAN=20
class=3Dsmallcode>sub</SPAN> instruction, but does not alter the source =
and=20
destination operands. Rules for the operands are the same as for the =
<SPAN=20
class=3Dsmallcode>sub</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>neg</SPAN> subtracts a =
signed integer=20
operand from zero. The effect of this instructon is to reverse the sign =
of the=20
operand from positive to negative or from negative to positive. Rules =
for the=20
operand are the same as for the <SPAN class=3Dsmallcode>inc</SPAN> =
instruction.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>xadd</SPAN> exchanges the =
destination=20
operand with the source operand, then loads the sum of the two values =
into the=20
destination operand. Rules for the operands are the same as for the =
<SPAN=20
class=3Dsmallcode>add</SPAN> instruction. </P>
<P class=3Dsmalltext>All the above binary arithmetic instructions update =
SF, ZF,=20
PF and OF flags. SF is always set to the same value as the result's sign =
bit, ZF=20
is set when all the bits of result are zero, PF is set when low order =
eight bits=20
of result contain an even number of set bits, OF is set if result is too =
large=20
for a positive number or too small for a negative number (excluding sign =
bit) to=20
fit in destination operand. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>mul</SPAN> performs an =
unsigned=20
multiplication of the operand and the accumulator. If the operand is a =
byte, the=20
processor multiplies it by the contents of AL and returns the 16-bit =
result to=20
AH and AL. If the operand is a word, the processor multiplies it by the =
contents=20
of AX and returns the 32-bit result to DX and AX. If the operand is a =
double=20
word, the processor multiplies it by the contents of EAX and returns the =
64-bit=20
result in EDX and EAX. <SPAN class=3Dsmallcode>mul</SPAN> sets CF and OF =
when the=20
upper half of the result is nonzero, otherwise they are cleared. Rules =
for the=20
operand are the same as for the <SPAN class=3Dsmallcode>inc</SPAN> =
instruction.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>imul</SPAN> performs a =
signed=20
multiplication operation. This instruction has three variations. First =
has one=20
operand and behaves in the same way as the <SPAN =
class=3Dsmallcode>mul</SPAN>=20
instruction. Second has two operands, in this case destination operand =
is=20
multiplied by the source operand and the result replaces the destination =

operand. Destination operand must be a general register, it can be word =
or=20
double word, source operand can be general register, memory or immediate =
value.=20
Third form has three operands, the destination operand must be a general =

register, word or double word in size, source operand can be general =
register or=20
memory, and third operand must be an immediate value. The source operand =
is=20
multiplied by the immediate value and the result is stored in the =
destination=20
register. All the three forms calculate the product to twice the size of =

operands and set CF and OF when the upper half of the result is nonzero, =
but=20
second and third form truncate the product to the size of operands. So =
second=20
and third forms can be also used for unsigned operands because, whether =
the=20
operands are signed or unsigned, the lower half of the product is the =
same.=20
Below are the examples for all three forms: </P><PRE class=3Dsmallcode>  =
  imul bl         ; accumulator by register
    imul word [si]  ; accumulator by memory
    imul bx,cx      ; register by register
    imul bx,[si]    ; register by memory
    imul bx,10      ; register by immediate value
    imul ax,bx,10   ; register by immediate value to register
    imul ax,[si],10 ; memory by immediate value to register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>div</SPAN> performs an =
unsigned=20
division of the accumulator by the operand. The dividend (the =
accumulator) is=20
twice the size of the divisor (the operand), the quotient and remainder =
have the=20
same size as the divisor. If divisor is byte, the dividend is taken from =
AX=20
register, the quotient is stored in AL and the remainder is stored in =
AH. If=20
divisor is word, the upper half of dividend is taken from DX, the lower =
half of=20
dividend is taken from AX, the quotient is stored in AX and the =
remainder is=20
stored in DX. If divisor is double word, the upper half of dividend is =
taken=20
from EDX, the lower half of dividend is taken from EAX, the quotient is =
stored=20
in EAX and the remainder is stored in EDX. Rules for the operand are the =
same as=20
for the <SPAN class=3Dsmallcode>mul</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>idiv</SPAN> performs a =
signed division=20
of the accumulator by the operand. It uses the same registers as the =
<SPAN=20
class=3Dsmallcode>div</SPAN> instruction, and the rules for the operand =
are the=20
same. </P>
<P><B><A class=3Dsmalltext name=3D2.1.4>2.1.4 Decimal arithmetic =
instructions</A>=20
</B></P>
<P class=3Dsmalltext>Decimal arithmetic is performed by combining the =
binary=20
arithmetic instructions (already described in the prior section) with =
the=20
decimal arithmetic instructions. The decimal arithmetic instructions are =
used to=20
adjust the results of a previous binary arithmetic operation to produce =
a valid=20
packed or unpacked decimal result, or to adjust the inputs to a =
subsequent=20
binary arithmetic operation so the operation will produce a valid packed =
or=20
unpacked decimal result. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>daa</SPAN> adjusts the =
result of adding=20
two valid packed decimal operands in AL. <SPAN =
class=3Dsmallcode>daa</SPAN> must=20
always follow the addition of two pairs of packed decimal numbers (one =
digit in=20
each half-byte) to obtain a pair of valid packed decimal digits as =
results. The=20
carry flag is set if carry was needed. This instruction has no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>das</SPAN> adjusts the =
result of=20
subtracting two valid packed decimal operands in AL. <SPAN=20
class=3Dsmallcode>das</SPAN> must always follow the subtraction of one =
pair of=20
packed decimal numbers (one digit in each half-byte) from another to =
obtain a=20
pair of valid packed decimal digits as results. The carry flag is set if =
a=20
borrow was needed. This instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aaa</SPAN> changes the =
contents of=20
register AL to a valid unpacked decimal number, and zeroes the top four =
bits.=20
<SPAN class=3Dsmallcode>aaa</SPAN> must always follow the addition of =
two unpacked=20
decimal operands in AL. The carry flag is set and AH is incremented if a =
carry=20
is necessary. This instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aas</SPAN> changes the =
contents of=20
register AL to a valid unpacked decimal number, and zeroes the top four =
bits.=20
<SPAN class=3Dsmallcode>aas</SPAN> must always follow the subtraction of =
one=20
unpacked decimal operand from another in AL. The carry flag is set and =
AH=20
decremented if a borrow is necessary. This instruction has no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aam</SPAN> corrects the =
result of a=20
multiplication of two valid unpacked decimal numbers. <SPAN=20
class=3Dsmallcode>aam</SPAN> must always follow the multiplication of =
two decimal=20
numbers to produce a valid decimal result. The high order digit is left =
in AH,=20
the low order digit in AL. The generalized version of this instruction =
allows=20
adjustment of the contents of the AX to create two unpacked digits of =
any number=20
base. The standard version of this instruction has no operands, the =
generalized=20
version has one operand - an immediate value specifying the number base =
for the=20
created digits. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aad</SPAN> modifies the =
numerator in AH=20
and AL to prepare for the division of two valid unpacked decimal =
operands so=20
that the quotient produced by the division will be a valid unpacked =
decimal=20
number. AH should contain the high order digit and AL the low order =
digit. This=20
instruction adjusts the value and places the result in AL, while AH will =
contain=20
zero. The generalized version of this instruction allows adjustment of =
two=20
unpacked digits of any number base. Rules for the operand are the same =
as for=20
the <SPAN class=3Dsmallcode>aam</SPAN> instruction. </P>
<P><B><A class=3Dsmalltext name=3D2.1.5>2.1.5 Logical instructions</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>not</SPAN> inverts the bits =
in the=20
specified operand to form a one's complement of the operand. It has no =
effect on=20
the flags. Rules for the operand are the same as for the <SPAN=20
class=3Dsmallcode>inc</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>and</SPAN>, <SPAN=20
class=3Dsmallcode>or</SPAN> and <SPAN class=3Dsmallcode>xor</SPAN> =
instructions=20
perform the standard logical operations. They update the SF, ZF and PF =
flags.=20
Rules for the operands are the same as for the <SPAN =
class=3Dsmallcode>add</SPAN>=20
instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bt</SPAN>, <SPAN=20
class=3Dsmallcode>bts</SPAN>, <SPAN class=3Dsmallcode>btr</SPAN> and =
<SPAN=20
class=3Dsmallcode>btc</SPAN> instructions operate on a single bit which =
can be in=20
memory or in a general register. The location of the bit is specified as =
an=20
offset from the low order end of the operand. The value of the offset is =
the=20
taken from the second operand, it either may be an immediate byte or a =
general=20
register. These instructions first assign the value of the selected bit =
to CF.=20
<SPAN class=3Dsmallcode>bt</SPAN> instruction does nothing more, <SPAN=20
class=3Dsmallcode>bts</SPAN> sets the selected bit to 1, <SPAN=20
class=3Dsmallcode>btr</SPAN> resets the selected bit to 0, <SPAN=20
class=3Dsmallcode>btc</SPAN> changes the bit to its complement. The =
first operand=20
can be word or double word. </P><PRE class=3Dsmallcode>    bt  ax,15     =
   ; test bit in register
    bts word [bx],15 ; test and set bit in memory
    btr ax,cx        ; test and reset bit in register
    btc word [bx],cx ; test and complement bit in memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bsf</SPAN> and <SPAN=20
class=3Dsmallcode>bsr</SPAN> instructions scan a word or double word for =
first set=20
bit and store the index of this bit into destination operand, which must =
be=20
general register. The bit string being scanned is specified by source =
operand,=20
it may be either general register or memory. The ZF flag is set if the =
entire=20
string is zero (no set bits are found); otherwise it is cleared. If no =
set bit=20
is found, the value of the destination register is undefined. <SPAN=20
class=3Dsmallcode>bsf</SPAN> scans from low order to high order =
(starting from bit=20
index zero). <SPAN class=3Dsmallcode>bsr</SPAN> scans from high order to =
low order=20
(starting from bit index 15 of a word or index 31 of a double word). =
</P><PRE class=3Dsmallcode>    bsf ax,bx        ; scan register forward
    bsr ax,[si]      ; scan memory reverse
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shl</SPAN> shifts the =
destination=20
operand left by the number of bits specified in the second operand. The=20
destination operand can be byte, word, or double word general register =
or=20
memory. The second operand can be an immediate value or the CL register. =
The=20
processor shifts zeros in from the right (low order) side of the operand =
as bits=20
exit from the left side. The last bit that exited is stored in CF. <SPAN =

class=3Dsmallcode>sal</SPAN> is a synonym for <SPAN =
class=3Dsmallcode>shl</SPAN>.=20
</P><PRE class=3Dsmallcode>    shl al,1         ; shift register left by =
one bit
    shl byte [bx],1  ; shift memory left by one bit
    shl ax,cl        ; shift register left by count from cl
    shl word [bx],cl ; shift memory left by count from cl
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shr</SPAN> and <SPAN=20
class=3Dsmallcode>sar</SPAN> shift the destination operand right by the =
number of=20
bits specified in the second operand. Rules for operands are the same as =
for the=20
<SPAN class=3Dsmallcode>shl</SPAN> instruction. <SPAN =
class=3Dsmallcode>shr</SPAN>=20
shifts zeros in from the left side of the operand as bits exit from the =
right=20
side. The last bit that exited is stored in CF. <SPAN =
class=3Dsmallcode>sar</SPAN>=20
preserves the sign of the operand by shifting in zeros on the left side =
if the=20
value is positive or by shifting in ones if the value is negative. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shld</SPAN> shifts bits of =
the=20
destination operand to the left by the number of bits specified in third =

operand, while shifting high order bits from the source operand into the =

destination operand on the right. The source operand remains unmodified. =
The=20
destination operand can be a word or double word general register or =
memory, the=20
source operand must be a general register, third operand can be an =
immediate=20
value or the CL register. </P><PRE class=3Dsmallcode>    shld ax,bx,1    =
 ; shift register left by one bit
    shld [di],bx,1   ; shift memory left by one bit
    shld ax,bx,cl    ; shift register left by count from cl
    shld [di],bx,cl  ; shift memory left by count from cl
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shrd</SPAN> shifts bits of =
the=20
destination operand to the right, while shifting low order bits from the =
source=20
operand into the destination operand on the left. The source operand =
remains=20
unmodified. Rules for operands are the same as for the <SPAN=20
class=3Dsmallcode>shld</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>rol</SPAN> and <SPAN=20
class=3Dsmallcode>rcl</SPAN> rotate the byte, word or double word =
destination=20
operand left by the number of bits specified in the second operand. For =
each=20
rotation specified, the high order bit that exits from the left of the =
operand=20
returns at the right to become the new low order bit. <SPAN=20
class=3Dsmallcode>rcl</SPAN> additionally puts in CF each high order bit =
that=20
exits from the left side of the operand before it returns to the operand =
as the=20
low order bit on the next rotation cycle. Rules for operands are the =
same as for=20
the <SPAN class=3Dsmallcode>shl</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ror</SPAN> and <SPAN=20
class=3Dsmallcode>rcr</SPAN> rotate the byte, word or double word =
destination=20
operand right by the number of bits specified in the second operand. For =
each=20
rotation specified, the low order bit that exits from the right of the =
operand=20
returns at the left to become the new high order bit. <SPAN=20
class=3Dsmallcode>rcr</SPAN> additionally puts in CF each low order bit =
that exits=20
from the right side of the operand before it returns to the operand as =
the high=20
order bit on the next rotation cycle. Rules for operands are the same as =
for the=20
<SPAN class=3Dsmallcode>shl</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>test</SPAN> performs the =
same action as=20
the <SPAN class=3Dsmallcode>and</SPAN> instruction, but it does not =
alter the=20
destination operand, only updates flags. Rules for the operands are the =
same as=20
for the <SPAN class=3Dsmallcode>and</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bswap</SPAN> reverses the =
byte order of=20
a 32-bit general register: bits 0 through 7 are swapped with bits 24 =
through 31,=20
and bits 8 through 15 are swapped with bits 16 through 23. This =
instruction is=20
provided for converting little-endian values to big-endian format and =
vice=20
versa. </P><PRE class=3Dsmallcode>    bswap edx        ; swap bytes in =
register
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.6>2.1.6 Control transfer =
instructions</A>=20
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>jmp</SPAN> unconditionally =
transfers=20
control to the target location. The destination address can be specified =

directly within the instruction or indirectly through a register or =
memory, the=20
acceptable size of this address depends on whether the jump is near or =
far (it=20
can be specified by preceding the operand with <SPAN =
class=3Dsmallcode>near</SPAN>=20
or <SPAN class=3Dsmallcode>far</SPAN> operator) and whether the =
instruction is=20
16-bit or 32-bit. Operand for near jump should be <SPAN=20
class=3Dsmallcode>word</SPAN> size for 16-bit instruction or the <SPAN=20
class=3Dsmallcode>dword</SPAN> size for 32-bit instruction. Operand for =
far jump=20
should be <SPAN class=3Dsmallcode>dword</SPAN> size for 16-bit =
instruction or=20
<SPAN class=3Dsmallcode>pword</SPAN> size for 32-bit instruction. A =
direct <SPAN=20
class=3Dsmallcode>jmp</SPAN> instruction includes the destination =
address as part=20
of the instruction (and can be preceded by <SPAN =
class=3Dsmallcode>short</SPAN>,=20
<SPAN class=3Dsmallcode>near</SPAN> or <SPAN =
class=3Dsmallcode>far</SPAN> operator),=20
the operand specifying address should be the numerical expression for =
near or=20
short jump, or two numerical expressions separated with colon for far =
jump, the=20
first specifies selector of segment, the second is the offset within =
segment.=20
The <SPAN class=3Dsmallcode>pword</SPAN> operator can be used to force =
the 32-bit=20
far call, and <SPAN class=3Dsmallcode>dword</SPAN> to force the 16-bit =
far call.=20
An indirect <SPAN class=3Dsmallcode>jmp</SPAN> instruction obtains the =
destination=20
address indirectly through a register or a pointer variable, the operand =
should=20
be general register or memory. See also 1.2.5 for some more details. =
</P><PRE class=3Dsmallcode>    jmp 100h         ; direct near jump
    jmp 0FFFFh:0     ; direct far jump
    jmp ax           ; indirect near jump
    jmp pword [ebx]  ; indirect far jump
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>call</SPAN> transfers =
control to the=20
procedure, saving on the stack the address of the instruction following =
the=20
<SPAN class=3Dsmallcode>call</SPAN> for later use by a <SPAN=20
class=3Dsmallcode>ret</SPAN> (return) instruction. Rules for the =
operands are the=20
same as for the <SPAN class=3Dsmallcode>jmp</SPAN> instruction, but the =
<SPAN=20
class=3Dsmallcode>call</SPAN> has no short variant of direct instruction =
and thus=20
it not optimized. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ret</SPAN>, <SPAN=20
class=3Dsmallcode>retn</SPAN> and <SPAN class=3Dsmallcode>retf</SPAN> =
instructions=20
terminate the execution of a procedure and transfers control back to the =
program=20
that originally invoked the procedure using the address that was stored =
on the=20
stack by the <SPAN class=3Dsmallcode>call</SPAN> instruction. <SPAN=20
class=3Dsmallcode>ret</SPAN> is the equivalent for <SPAN=20
class=3Dsmallcode>retn</SPAN>, which returns from the procedure that was =
executed=20
using the near call, while <SPAN class=3Dsmallcode>retf</SPAN> returns =
from the=20
procedure that was executed using the far call. These instructions =
default to=20
the size of address appropriate for the current code setting, but the =
size of=20
address can be forced to 16-bit by using the <SPAN =
class=3Dsmallcode>retw</SPAN>,=20
<SPAN class=3Dsmallcode>retnw</SPAN> and <SPAN =
class=3Dsmallcode>retfw</SPAN>=20
mnemonics, and to 32-bit by using the <SPAN =
class=3Dsmallcode>retd</SPAN>, <SPAN=20
class=3Dsmallcode>retnd</SPAN> and <SPAN class=3Dsmallcode>retfd</SPAN> =
mnemonics.=20
All these instructions may optionally specify an immediate operand, by =
adding=20
this constant to the stack pointer, they effectively remove any =
arguments that=20
the calling program pushed on the stack before the execution of the =
<SPAN=20
class=3Dsmallcode>call</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>iret</SPAN> returns control =
to an=20
interrupted procedure. It differs from <SPAN =
class=3Dsmallcode>ret</SPAN> in that=20
it also pops the flags from the stack into the flags register. The flags =
are=20
stored on the stack by the interrupt mechanism. It defaults to the size =
of=20
return address appropriate for the current code setting, but it can be =
forced to=20
use 16-bit or 32-bit address by using the <SPAN =
class=3Dsmallcode>iretw</SPAN> or=20
<SPAN class=3Dsmallcode>iretd</SPAN> mnemonic. </P>
<P class=3Dsmalltext>The conditional transfer instructions are jumps =
that may or=20
may not transfer control, depending on the state of the CPU flags when =
the=20
instruction executes. The mnemonics for conditional jumps may be =
obtained by=20
attaching the condition mnemonic (see table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.1">2.1</A>)=
 to the=20
<SPAN class=3Dsmallcode>j</SPAN> mnemonic, for example <SPAN=20
class=3Dsmallcode>jc</SPAN> instruction will transfer the control when =
the CF flag=20
is set. The conditional jumps can be short or near, and direct only, and =
can be=20
optimized (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.5">1.2.5</=
A>), the=20
operand should be an immediate value specifying target address. </P>
<P class=3Dsmalltext><B><A name=3D_2.1>Table 2.1 Conditions</A></B> </P>
<TABLE style=3D"WIDTH: 400px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Mnemonic</TH>
    <TH>Condition tested</TH>
    <TH>Description</TH></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>o</SPAN></TD>
    <TD>OF =3D 1</TD>
    <TD>overflow</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>no</SPAN></TD>
    <TD>OF =3D 0</TD>
    <TD>not overflow</TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>c</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>b</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nae</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>CF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>carry</TD></TR>
        <TR>
          <TD>below</TD></TR>
        <TR>
          <TD>not above nor equal</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>nc</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ae</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nb</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>CF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>not carry</TD></TR>
        <TR>
          <TD>above or equal</TD></TR>
        <TR>
          <TD>not below</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>e</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>z</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>ZF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>equal</TD></TR>
        <TR>
          <TD>zero</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>ne</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nz</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>ZF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>not equal</TD></TR>
        <TR>
          <TD>not zero</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>be</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>na</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>CF <SPAN class=3Dsmallcode>or</SPAN> ZF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>below or equal</TD></TR>
        <TR>
          <TD>not above</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>a</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nbe</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>CF <SPAN class=3Dsmallcode>or</SPAN> ZF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>above</TD></TR>
        <TR>
          <TD>not below nor equal</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>s</SPAN></TD>
    <TD>SF =3D 1</TD>
    <TD>sign</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>ns</SPAN></TD>
    <TD>SF =3D 0</TD>
    <TD>not sign</TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>p</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>pe</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>PF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>parity</TD></TR>
        <TR>
          <TD>parity even</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>np</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>po</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>PF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>not parity</TD></TR>
        <TR>
          <TD>parity odd</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>l</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nge</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>SF <SPAN class=3Dsmallcode>xor</SPAN> OF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>less</TD></TR>
        <TR>
          <TD>not greater nor equal</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>ge</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nl</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>SF <SPAN class=3Dsmallcode>xor</SPAN> OF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>greater or equal</TD></TR>
        <TR>
          <TD>not less</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>le</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>ng</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>(SF <SPAN class=3Dsmallcode>xor</SPAN> OF) <SPAN=20
      class=3Dsmallcode>or</SPAN> ZF =3D 1</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>less or equal</TD></TR>
        <TR>
          <TD>not greater</TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>g</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>nle</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>(SF <SPAN class=3Dsmallcode>xor</SPAN> OF) <SPAN=20
      class=3Dsmallcode>or</SPAN> ZF =3D 0</TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD>greater</TD></TR>
        <TR>
          <TD>not less nor =
equal</TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>loop</SPAN> =
instructions are=20
conditional jumps that use a value placed in CX (or ECX) to specify the =
number=20
of repetitions of a software loop. All <SPAN =
class=3Dsmallcode>loop</SPAN>=20
instructions automatically decrement CX (or ECX) and terminate the loop =
(don't=20
transfer the control) when CX (or ECX) is zero. It uses CX or ECX =
whether the=20
current code setting is 16-bit or 32-bit, but it can be forced to us CX =
with the=20
<SPAN class=3Dsmallcode>loopw</SPAN> mnemonic or to use ECX with the =
<SPAN=20
class=3Dsmallcode>loopd</SPAN> mnemonic. <SPAN =
class=3Dsmallcode>loope</SPAN> and=20
<SPAN class=3Dsmallcode>loopz</SPAN> are the synonyms for the same =
instruction,=20
which acts as the standard <SPAN class=3Dsmallcode>loop</SPAN>, but also =

terminates the loop when ZF flag is set. <SPAN =
class=3Dsmallcode>loopew</SPAN> and=20
<SPAN class=3Dsmallcode>loopzw</SPAN> mnemonics force them to use CX =
register=20
while <SPAN class=3Dsmallcode>looped</SPAN> and <SPAN=20
class=3Dsmallcode>loopzd</SPAN> force them to use ECX register. <SPAN=20
class=3Dsmallcode>loopne</SPAN> and <SPAN =
class=3Dsmallcode>loopnz</SPAN> are the=20
synonyms for the same instructions, which acts as the standard <SPAN=20
class=3Dsmallcode>loop</SPAN>, but also terminate the loop when ZF flag =
is not=20
set. <SPAN class=3Dsmallcode>loopnew</SPAN> and <SPAN=20
class=3Dsmallcode>loopnzw</SPAN> mnemonics force them to use CX register =
while=20
<SPAN class=3Dsmallcode>loopned</SPAN> and <SPAN =
class=3Dsmallcode>loopnzd</SPAN>=20
force them to use ECX register. Every <SPAN =
class=3Dsmallcode>loop</SPAN>=20
instruction needs an operand being an immediate value specifying target =
address,=20
it can be only short jump (in the range of 128 bytes back and 127 bytes =
forward=20
from the address of instruction following the <SPAN =
class=3Dsmallcode>loop</SPAN>=20
instruction). </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>jcxz</SPAN> branches to the =
label=20
specified in the instruction if it finds a value of zero in CX, <SPAN=20
class=3Dsmallcode>jecxz</SPAN> does the same, but checks the value of =
ECX instead=20
of CX. Rules for the operands are the same as for the <SPAN=20
class=3Dsmallcode>loop</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>int</SPAN> activates the =
interrupt=20
service routine that corresponds to the number specified as an operand =
to the=20
instruction, the number should be in range from 0 to 255. The interrupt =
service=20
routine terminates with an <SPAN class=3Dsmallcode>iret</SPAN> =
instruction that=20
returns control to the instruction that follows <SPAN=20
class=3Dsmallcode>int</SPAN>. <SPAN class=3Dsmallcode>int3</SPAN> =
mnemonic codes the=20
short (one byte) trap that invokes the interrupt 3. <SPAN=20
class=3Dsmallcode>into</SPAN> instruction invokes the interrupt 4 if the =
OF flag=20
is set. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bound</SPAN> verifies that =
the signed=20
value contained in the specified register lies within specified limits. =
An=20
interrupt 5 occurs if the value contained in the register is less than =
the lower=20
bound or greater than the upper bound. It needs two operands, the first =
operand=20
specifies the register being tested, the second operand should be memory =
address=20
for the two signed limit values. The operands can be <SPAN=20
class=3Dsmallcode>word</SPAN> or <SPAN class=3Dsmallcode>dword</SPAN> in =
size. </P><PRE class=3Dsmallcode>    bound ax,[bx]    ; check word for =
bounds
    bound eax,[esi]  ; check double word for bounds
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.7>2.1.7 I/O instructions</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>in</SPAN> transfers a byte, =
word, or=20
double word from an input port to AL, AX, or EAX. I/O ports can be =
addressed=20
either directly, with the immediate byte value coded in instruction, or=20
indirectly via the DX register. The destination operand should be AL, =
AX, or EAX=20
register. The source operand should be an immediate value in range from =
0 to=20
255, or DX register. </P><PRE class=3Dsmallcode>    in al,20h        ; =
input byte from port 20h
    in ax,dx         ; input word from port addressed by dx
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>out</SPAN> transfers a =
byte, word, or=20
double word to an output port from AL, AX, or EAX. The program can =
specify the=20
number of the port using the same methods as the <SPAN =
class=3Dsmallcode>in</SPAN>=20
instruction. The destination operand should be an immediate value in =
range from=20
0 to 255, or DX register. The source operand should be AL, AX, or EAX =
register.=20
</P><PRE class=3Dsmallcode>    out 20h,ax       ; output word to port =
20h
    out dx,al        ; output byte to port addressed by dx
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.8>2.1.8 Strings operations</A> =
</B></P>
<P class=3Dsmalltext>The string operations operate on one element of a =
string. A=20
string element may be a byte, a word, or a double word. The string =
elements are=20
addressed by SI and DI (or ESI and EDI) registers. After every string =
operation=20
SI and/or DI (or ESI and/or EDI) are automatically updated to point to =
the next=20
element of the string. If DF (direction flag) is zero, the index =
registers are=20
incremented, if DF is one, they are decremented. The amount of the =
increment or=20
decrement is 1, 2, or 4 depending on the size of the string element. =
Every=20
string operation instruction has short forms which have no operands and =
use SI=20
and/or DI when the code type is 16-bit, and ESI and/or EDI when the code =
type is=20
32-bit. SI and ESI by default address data in the segment selected by =
DS, DI and=20
EDI always address data in the segment selected by ES. Short form is =
obtained by=20
attaching to the mnemonic of string operation letter specifying the size =
of=20
string element, it should be <SPAN class=3Dsmallcode>b</SPAN> for byte =
element,=20
<SPAN class=3Dsmallcode>w</SPAN> for word element, and <SPAN=20
class=3Dsmallcode>d</SPAN> for double word element. Full form of string =
operation=20
needs operands providing the size operator and the memory addresses, =
which can=20
be SI or ESI with any segment prefix, DI or EDI always with ES segment =
prefix.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movs</SPAN> transfers the =
string=20
element pointed to by SI (or ESI) to the location pointed to by DI (or =
EDI).=20
Size of operands can be byte, word, or double word. The destination =
operand=20
should be memory addressed by DI or EDI, the source operand should be =
memory=20
addressed by SI or ESI with any segment prefix. </P><PRE =
class=3Dsmallcode>    movs byte [di],[si]        ; transfer byte
    movs word [es:di],[ss:si]  ; transfer word
    movsd                      ; transfer double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmps</SPAN> subtracts the =
destination=20
string element from the source string element and updates the flags AF, =
SF, PF,=20
CF and OF, but it does not change any of the compared elements. If the =
string=20
elements are equal, ZF is set, otherwise it is cleared. The first =
operand for=20
this instruction should be the source string element addressed by SI or =
ESI with=20
any segment prefix, the second operand should be the destination string =
element=20
addressed by DI or EDI. </P><PRE class=3Dsmallcode>    cmpsb             =
         ; compare bytes
    cmps word [ds:si],[es:di]  ; compare words
    cmps dword [fs:esi],[edi]  ; compare double words
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>scas</SPAN> subtracts the =
destination=20
string element from AL, AX, or EAX (depending on the size of string =
element) and=20
updates the flags AF, SF, ZF, PF, CF and OF. If the values are equal, ZF =
is set,=20
otherwise it is cleared. The operand should be the destination string =
element=20
addressed by DI or EDI. </P><PRE class=3Dsmallcode>    scas byte [es:di] =
         ; scan byte
    scasw                      ; scan word
    scas dword [es:edi]        ; scan double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>stos</SPAN> places the =
value of AL, AX,=20
or EAX into the destination string element. Rules for the operand are =
the same=20
as for the <SPAN class=3Dsmallcode>scas</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lods</SPAN> places the =
source string=20
element into AL, AX, or EAX. The operand should be the source string =
element=20
addressed by SI or ESI with any segment prefix. </P><PRE =
class=3Dsmallcode>    lods byte [ds:si]           ; load byte
    lods word [cs:si]           ; load word
    lodsd                       ; load double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ins</SPAN> transfers a =
byte, word, or=20
double word from an input port addressed by DX register to the =
destination=20
string element. The destination operand should be memory addressed by DI =
or EDI,=20
the source operand should be the DX register. </P><PRE =
class=3Dsmallcode>    insb                       ; input byte
    ins word [es:di],dx        ; input word
    ins dword [edi],dx         ; input double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>outs</SPAN> transfers the =
source string=20
element to an output port addressed by DX register. The destination =
operand=20
should be the DX register and the source operand should be memory =
addressed by=20
SI or ESI with any segment prefix. </P><PRE class=3Dsmallcode>    outs =
dx,byte [si]          ; output byte
    outsw                      ; output word
    outs dx,dword [gs:esi]     ; output double word
</PRE>
<P class=3Dsmalltext>The repeat prefixes <SPAN =
class=3Dsmallcode>rep</SPAN>, <SPAN=20
class=3Dsmallcode>repe</SPAN>/<SPAN class=3Dsmallcode>repz</SPAN>, and =
<SPAN=20
class=3Dsmallcode>repne</SPAN>/<SPAN class=3Dsmallcode>repnz</SPAN> =
specify repeated=20
string operation. When a string operation instruction has a repeat =
prefix, the=20
operation is executed repeatedly, each time using a different element of =
the=20
string. The repetition terminates when one of the conditions specified =
by the=20
prefix is satisfied. All three prefixes automatically decrease CX or ECX =

register (depending whether string operation instruction uses the 16-bit =
or=20
32-bit addressing) after each operation and repeat the associated =
operation=20
until CX or ECX is zero. <SPAN class=3Dsmallcode>repe</SPAN>/<SPAN=20
class=3Dsmallcode>repz</SPAN> and <SPAN =
class=3Dsmallcode>repne</SPAN>/<SPAN=20
class=3Dsmallcode>repnz</SPAN> are used exclusively with the <SPAN=20
class=3Dsmallcode>scas</SPAN> and <SPAN class=3Dsmallcode>cmps</SPAN> =
instructions=20
(described below). When these prefixes are used, repetition of the next=20
instruction depends on the zero flag (ZF) also, <SPAN=20
class=3Dsmallcode>repe</SPAN> and <SPAN class=3Dsmallcode>repz</SPAN> =
terminate the=20
execution when the ZF is zero, <SPAN class=3Dsmallcode>repne</SPAN> and =
<SPAN=20
class=3Dsmallcode>repnz</SPAN> terminate the execution when the ZF is =
set. </P><PRE class=3Dsmallcode>    rep  movsd       ; transfer multiple =
double words
    repe cmpsb       ; compare bytes until not equal
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.9>2.1.9 Flag control =
instructions</A> </B></P>
<P class=3Dsmalltext>The flag control instructions provide a method for =
directly=20
changing the state of bits in the flag register. All instructions =
described in=20
this section have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>stc</SPAN> sets the CF =
(carry flag) to=20
1, <SPAN class=3Dsmallcode>clc</SPAN> zeroes the CF, <SPAN=20
class=3Dsmallcode>cmc</SPAN> changes the CF to its complement. <SPAN=20
class=3Dsmallcode>std</SPAN> sets the DF (direction flag) to 1, <SPAN=20
class=3Dsmallcode>cld</SPAN> zeroes the DF, <SPAN =
class=3Dsmallcode>sti</SPAN> sets=20
the IF (interrupt flag) to 1 and therefore enables the interrupts, <SPAN =

class=3Dsmallcode>cli</SPAN> zeroes the IF and therefore disables the =
interrupts.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lahf</SPAN> copies SF, ZF, =
AF, PF, and=20
CF to bits 7, 6, 4, 2, and 0 of the AH register. The contents of the =
remaining=20
bits are undefined. The flags remain unaffected. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>sahf</SPAN> transfers bits =
7, 6, 4, 2,=20
and 0 from the AH register into SF, ZF, AF, PF, and CF. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pushf</SPAN> decrements =
<SPAN=20
class=3Dsmallcode>esp</SPAN> by two or four and stores the low word or =
double word=20
of flags register at the top of stack, size of stored data depends on =
the=20
current code setting. <SPAN class=3Dsmallcode>pushfw</SPAN> variant =
forces storing=20
the word and <SPAN class=3Dsmallcode>pushfd</SPAN> forces storing the =
double word.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>popf</SPAN> transfers =
specific bits=20
from the word or double word at the top of stack, then increments <SPAN=20
class=3Dsmallcode>esp</SPAN> by two or four, this value depends on the =
current=20
code setting. <SPAN class=3Dsmallcode>popfw</SPAN> variant forces =
restoring from=20
the word and <SPAN class=3Dsmallcode>popfd</SPAN> forces restoring from =
the double=20
word. </P>
<P><B><A class=3Dsmalltext name=3D2.1.10>2.1.10 Conditional =
operations</A> </B></P>
<P class=3Dsmalltext>The instructions obtained by attaching the =
condition mnemonic=20
(see table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.1">2.1</A>)=
 to the=20
<SPAN class=3Dsmallcode>set</SPAN> mnemonic set a byte to one if the =
condition is=20
true and set the byte to zero otherwise. The operand should be an 8-bit =
be=20
general register or the byte in memory. </P><PRE class=3Dsmallcode>    =
setne al         ; set al if zero flag cleared
    seto byte [bx]   ; set byte if overflow
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>salc</SPAN> instruction =
sets the all=20
bits of AL register when the carry flag is set and zeroes the AL =
register=20
otherwise. This instruction has no arguments. </P>
<P class=3Dsmalltext>The instructions obtained by attaching the =
condition mnemonic=20
to <SPAN class=3Dsmallcode>cmov</SPAN> mnemonic transfer the word or =
double word=20
from the general register or memory to the general register only when =
the=20
condition is true. The destination operand should be general register, =
the=20
source operand can be general register or memory. </P><PRE =
class=3Dsmallcode>    cmove ax,bx      ; move when zero flag set
    cmovnc eax,[ebx] ; move when carry flag cleared
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmpxchg</SPAN> compares the =
value in=20
the AL, AX, or EAX register with the destination operand. If the two =
values are=20
equal, the source operand is loaded into the destination operand. =
Otherwise, the=20
destination operand is loaded into the AL, AX, or EAX register. The =
destination=20
operand may be a general register or memory, the source operand must be =
a=20
general register. </P><PRE class=3Dsmallcode>    cmpxchg dl,bl    ; =
compare and exchange with register
    cmpxchg [bx],dx  ; compare and exchange with memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmpxchg8b</SPAN> compares =
the 64-bit=20
value in EDX and EAX registers with the destination operand. If the =
values are=20
equal, the 64-bit value in ECX and EBX registers is stored in the =
destination=20
operand. Otherwise, the value in the destination operand is loaded into =
EDX and=20
EAX registers. The destination operand should be a quad word in memory. =
</P><PRE class=3Dsmallcode>    cmpxchg8b [bx]   ; compare and exchange 8 =
bytes
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.11>2.1.11 Miscellaneous =
instructions</A>=20
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>nop</SPAN> instruction =
occupies one=20
byte but affects nothing but the instruction pointer. This instruction =
has no=20
operands and doesn't perform any operation. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ud2</SPAN> instruction =
generates an=20
invalid opcode exception. This instruction is provided for software =
testing to=20
explicitly generate an invalid opcode. This is instruction has no =
operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>xlat</SPAN> replaces a byte =
in the AL=20
register with a byte indexed by its value in a translation table =
addressed by BX=20
or EBX. The operand should be a byte memory addressed by BX or EBX with =
any=20
segment prefix. This instruction has also a short form <SPAN=20
class=3Dsmallcode>xlatb</SPAN> which has no operands and uses the BX or =
EBX=20
address in the segment selected by DS depending on the current code =
setting.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lds</SPAN> transfers a =
pointer variable=20
from the source operand to DS and the destination register. The source =
operand=20
must be a memory operand, and the destination operand must be a general=20
register. The DS register receives the segment selector of the pointer =
while the=20
destination register receives the offset part of the pointer. <SPAN=20
class=3Dsmallcode>les</SPAN>, <SPAN class=3Dsmallcode>lfs</SPAN>, <SPAN=20
class=3Dsmallcode>lgs</SPAN> and <SPAN class=3Dsmallcode>lss</SPAN> =
operate=20
identically to <SPAN class=3Dsmallcode>lds</SPAN> except that rather =
than DS=20
register the ES, FS, GS and SS is used respectively. </P><PRE =
class=3Dsmallcode>    lds bx,[si]      ; load pointer to ds:bx
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lea</SPAN> transfers the =
offset of the=20
source operand (rather than its value) to the destination operand. The =
source=20
operand must be a memory operand, and the destination operand must be a =
general=20
register. </P><PRE class=3Dsmallcode>    lea dx,[bx+si+1] ; load =
effective address to dx
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cpuid</SPAN> returns =
processor=20
identification and feature information in the EAX, EBX, ECX, and EDX =
registers.=20
The information returned is selected by entering a value in the EAX =
register=20
before the instruction is executed. This instruction has no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pause</SPAN> instruction =
delays the=20
execution of the next instruction an implementation specific amount of =
time. It=20
can be used to improve the performance of spin wait loops. This =
instruction has=20
no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>enter</SPAN> creates a =
stack frame that=20
may be used to implement the scope rules of block-structured high-level=20
languages. A <SPAN class=3Dsmallcode>leave</SPAN> instruction at the end =
of a=20
procedure complements an <SPAN class=3Dsmallcode>enter</SPAN> at the =
beginning of=20
the procedure to simplify stack management and to control access to =
variables=20
for nested procedures. The <SPAN class=3Dsmallcode>enter</SPAN> =
instruction=20
includes two parameters. The first parameter specifies the number of =
bytes of=20
dynamic storage to be allocated on the stack for the routine being =
entered. The=20
second parameter corresponds to the lexical nesting level of the =
routine, it can=20
be in range from 0 to 31. The specified lexical level determines how =
many sets=20
of stack frame pointers the CPU copies into the new stack frame from the =

preceding frame. This list of stack frame pointers is sometimes called =
the=20
display. The first word (or double word when code is 32-bit) of the =
display is a=20
pointer to the last stack frame. This pointer enables a <SPAN=20
class=3Dsmallcode>leave</SPAN> instruction to reverse the action of the =
previous=20
<SPAN class=3Dsmallcode>enter</SPAN> instruction by effectively =
discarding the=20
last stack frame. After <SPAN class=3Dsmallcode>enter</SPAN> creates the =
new=20
display for a procedure, it allocates the dynamic storage space for that =

procedure by decrementing ESP by the number of bytes specified in the =
first=20
parameter. To enable a procedure to address its display, <SPAN=20
class=3Dsmallcode>enter</SPAN> leaves BP (or EBP) pointing to the =
beginning of the=20
new stack frame. If the lexical level is zero, <SPAN=20
class=3Dsmallcode>enter</SPAN> pushes BP (or EBP), copies SP to BP (or =
ESP to EBP)=20
and then subtracts the first operand from ESP. For nesting levels =
greater than=20
zero, the processor pushes additional frame pointers on the stack before =

adjusting the stack pointer. </P><PRE class=3Dsmallcode>    enter 2048,0 =
    ; enter and allocate 2048 bytes on stack
</PRE>
<P><B><A class=3Dsmalltext name=3D2.1.12>2.1.12 System instructions</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lmsw</SPAN> loads the =
operand into the=20
machine status word (bits 0 through 15 of CR0 register), while <SPAN=20
class=3Dsmallcode>smsw</SPAN> stores the machine status word into the =
destination=20
operand. The operand for both those instructions can be 16-bit general =
register=20
or memory, for <SPAN class=3Dsmallcode>smsw</SPAN> it can also be 32-bit =
general=20
register. </P><PRE class=3Dsmallcode>    lmsw ax          ; load machine =
status from register
    smsw [bx]        ; store machine status to memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lgdt</SPAN> and <SPAN=20
class=3Dsmallcode>lidt</SPAN> instructions load the values in operand =
into the=20
global descriptor table register or the interrupt descriptor table =
register=20
respectively. <SPAN class=3Dsmallcode>sgdt</SPAN> and <SPAN=20
class=3Dsmallcode>sidt</SPAN> store the contents of the global =
descriptor table=20
register or the interrupt descriptor table register in the destination =
operand.=20
The operand should be a 6 bytes in memory. </P><PRE class=3Dsmallcode>   =
 lgdt [ebx]       ; load global descriptor table
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lldt</SPAN> loads the =
operand into the=20
segment selector field of the local descriptor table register and <SPAN=20
class=3Dsmallcode>sldt</SPAN> stores the segment selector from the local =

descriptor table register in the operand. <SPAN =
class=3Dsmallcode>ltr</SPAN> loads=20
the operand into the segment selector field of the task register and =
<SPAN=20
class=3Dsmallcode>str</SPAN> stores the segment selector from the task =
register in=20
the operand. Rules for operand are the same as for the <SPAN=20
class=3Dsmallcode>lmsw</SPAN> and <SPAN class=3Dsmallcode>smsw</SPAN> =
instructions.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lar</SPAN> loads the access =
rights from=20
the segment descriptor specified by the selector in source operand into =
the=20
destination operand and sets the ZF flag. The destination operand can be =
a=20
16-bit or 32-bit general register. The source operand should be a 16-bit =
general=20
register or memory. </P><PRE class=3Dsmallcode>    lar ax,[bx]      ; =
load access rights into word
    lar eax,dx       ; load access rights into double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lsl</SPAN> loads the =
segment limit from=20
the segment descriptor specified by the selector in source operand into =
the=20
destination operand and sets the ZF flag. Rules for operand are the same =
as for=20
the <SPAN class=3Dsmallcode>lar</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>verr</SPAN> and <SPAN=20
class=3Dsmallcode>verw</SPAN> verify whether the code or data segment =
specified=20
with the operand is readable or writable from the current privilege =
level. The=20
operand should be a word, it can be general register or memory. If the =
segment=20
is accessible and readable (for <SPAN class=3Dsmallcode>verr</SPAN>) or =
writable=20
(for <SPAN class=3Dsmallcode>verw</SPAN>) the ZF flag is set, otherwise =
it's=20
cleared. Rules for operand are the same as for the <SPAN=20
class=3Dsmallcode>lldt</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>arpl</SPAN> compares the =
RPL=20
(requestor's privilege level) fields of two segment selectors. The first =
operand=20
contains one segment selector and the second operand contains the other. =
If the=20
RPL field of the destination operand is less than the RPL field of the =
source=20
operand, the ZF flag is set and the RPL field of the destination operand =
is=20
increased to match that of the source operand. Otherwise, the ZF flag is =
cleared=20
and no change is made to the destination operand. The destination =
operand can be=20
a word general register or memory, the source operand must be a general=20
register. </P><PRE class=3Dsmallcode>    arpl bx,ax       ; adjust RPL =
of selector in register
    arpl [bx],ax     ; adjust RPL of selector in memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>clts</SPAN> clears the TS =
(task=20
switched) flag in the CR0 register. This instruction has no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lock</SPAN> prefix causes =
the=20
processor's bus-lock signal to be asserted during execution of the =
accompanying=20
instruction. In a multiprocessor environment, the bus-lock signal =
insures that=20
the processor has exclusive use of any shared memory while the signal is =

asserted. The <SPAN class=3Dsmallcode>lock</SPAN> prefix can be =
prepended only to=20
the following instructions and only to those forms of the instructions =
where the=20
destination operand is a memory operand: <SPAN =
class=3Dsmallcode>add</SPAN>, <SPAN=20
class=3Dsmallcode>adc</SPAN>, <SPAN class=3Dsmallcode>and</SPAN>, <SPAN=20
class=3Dsmallcode>btc</SPAN>, <SPAN class=3Dsmallcode>btr</SPAN>, <SPAN=20
class=3Dsmallcode>bts</SPAN>, <SPAN class=3Dsmallcode>cmpxchg</SPAN>, =
<SPAN=20
class=3Dsmallcode>cmpxchg8b</SPAN>, <SPAN class=3Dsmallcode>dec</SPAN>, =
<SPAN=20
class=3Dsmallcode>inc</SPAN>, <SPAN class=3Dsmallcode>neg</SPAN>, <SPAN=20
class=3Dsmallcode>not</SPAN>, <SPAN class=3Dsmallcode>or</SPAN>, <SPAN=20
class=3Dsmallcode>sbb</SPAN> <SPAN class=3Dsmallcode>sub</SPAN>, <SPAN=20
class=3Dsmallcode>xor</SPAN>, <SPAN class=3Dsmallcode>xadd</SPAN> and =
<SPAN=20
class=3Dsmallcode>xchg</SPAN>. If the <SPAN =
class=3Dsmallcode>lock</SPAN> prefix is=20
used with one of these instructions and the source operand is a memory =
operand,=20
an undefined opcode exception may be generated. An undefined opcode =
exception=20
will also be generated if the <SPAN class=3Dsmallcode>lock</SPAN> prefix =
is used=20
with any instruction not in the above list. The <SPAN=20
class=3Dsmallcode>xchg</SPAN> instruction always asserts the bus-lock =
signal=20
regardless of the presence or absence of the <SPAN =
class=3Dsmallcode>lock</SPAN>=20
prefix. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>hlt</SPAN> stops =
instruction execution=20
and places the processor in a halted state. An enabled interrupt, a =
debug=20
exception, the BINIT, INIT or the RESET signal will resume execution. =
This=20
instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>invlpg</SPAN> invalidates =
(flushes) the=20
TLB (translation lookaside buffer) entry specified with the operand, =
which=20
should be a memory. The processor determines the page that contains that =
address=20
and flushes the TLB entry for that page. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>rdmsr</SPAN> loads the =
contents of a=20
64-bit MSR (model specific register) of the address specified in the ECX =

register into registers EDX and EAX. <SPAN =
class=3Dsmallcode>wrmsr</SPAN> writes=20
the contents of registers EDX and EAX into the 64-bit MSR of the address =

specified in the ECX register. <SPAN class=3Dsmallcode>rdtsc</SPAN> =
loads the=20
current value of the processor's time stamp counter from the 64-bit MSR =
into the=20
EDX and EAX registers. The processor increments the time stamp counter =
MSR every=20
clock cycle and resets it to 0 whenever the processor is reset. <SPAN=20
class=3Dsmallcode>rdpmc</SPAN> loads the contents of the 40-bit =
performance=20
monitoring counter specified in the ECX register into registers EDX and =
EAX.=20
These instructions have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>wbinvd</SPAN> writes back =
all modified=20
cache lines in the processor's internal cache to main memory and =
invalidates=20
(flushes) the internal caches. The instruction then issues a special =
function=20
bus cycle that directs external caches to also write back modified data =
and=20
another bus cycle to indicate that the external caches should be =
invalidated.=20
This instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>rsm</SPAN> return program =
control from=20
the system management mode to the program that was interrupted when the=20
processor received an SMM interrupt. This instruction has no operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>sysenter</SPAN> executes a =
fast call to=20
a level 0 system procedure, <SPAN class=3Dsmallcode>sysexit</SPAN> =
executes a fast=20
return to level 3 user code. The addresses used by these instructions =
are stored=20
in MSRs. These instructions have no operands. </P>
<P><B><A class=3Dsmalltext name=3D2.1.13>2.1.13 FPU instructions</A> =
</B></P>
<P class=3Dsmalltext>The FPU (Floating-Point Unit) instructions operate =
on the=20
floating-point values in three formats: single precision (32-bit), =
double=20
precision (64-bit) and double extended precision (80-bit). The FPU =
registers=20
form the stack and each of them holds the double extended precision=20
floating-point value. When some values are pushed onto the stack or are =
removed=20
from the top, the FPU registers are shifted, so ST0 is always the value =
on the=20
top of FPU stack, ST1 is the first value below the top, etc. The ST0 =
name has=20
also the synonym ST. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fld</SPAN> pushes the =
floating-point=20
value onto the FPU register stack. The operand can be 32-bit, 64-bit or =
80-bit=20
memory location or the FPU register, it's value is then loaded onto the =
top of=20
FPU register stack (the ST0 register) and is automatically converted =
into the=20
double extended precision format. </P><PRE class=3Dsmallcode>    fld =
dword [bx]   ; load single prevision value from memory
    fld st2          ; push value of st2 onto register stack
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fld1</SPAN>, <SPAN=20
class=3Dsmallcode>fldz</SPAN>, <SPAN class=3Dsmallcode>fldl2t</SPAN>, =
<SPAN=20
class=3Dsmallcode>fldl2e</SPAN>, <SPAN class=3Dsmallcode>fldpi</SPAN>, =
<SPAN=20
class=3Dsmallcode>fldlg2</SPAN> and <SPAN =
class=3Dsmallcode>fldln2</SPAN> load the=20
commonly used contants onto the FPU register stack. The loaded constants =
are=20
+1.0, +0.0, log<SUB>2</SUB>10, log<SUB>2</SUB>e, =CF=80, =
log<SUB>10</SUB>2 and ln 2=20
respectively. These instructions have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fild</SPAN> converts the =
signed integer=20
source operand into double extended precision floating-point format and =
pushes=20
the result onto the FPU register stack. The source operand can be a =
16-bit,=20
32-bit or 64-bit memory location. </P><PRE class=3Dsmallcode>    fild =
qword [bx]  ; load 64-bit integer from memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fst</SPAN> copies the value =
of ST0=20
register to the destination operand, which can be 32-bit or 64-bit =
memory=20
location or another FPU register. <SPAN class=3Dsmallcode>fstp</SPAN> =
performs the=20
same operation as <SPAN class=3Dsmallcode>fst</SPAN> and then pops the =
register=20
stack, getting rid of ST0. <SPAN class=3Dsmallcode>fstp</SPAN> accepts =
the same=20
operands as the <SPAN class=3Dsmallcode>fst</SPAN> instruction and can =
also store=20
value in the 80-bit memory. </P><PRE class=3Dsmallcode>    fst st3       =
   ; copy value of st0 into st3 register
    fstp tword [bx]  ; store value in memory and pop stack
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fist</SPAN> converts the =
value in ST0=20
to a signed integer and stores the result in the destination operand. =
The=20
operand can be 16-bit or 32-bit memory location. <SPAN=20
class=3Dsmallcode>fistp</SPAN> performs the same operation and then pops =
the=20
register stack, it accepts the same operands as the <SPAN=20
class=3Dsmallcode>fist</SPAN> instruction and can also store integer =
value in the=20
64-bit memory, so it has the same rules for operands as <SPAN=20
class=3Dsmallcode>fild</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fbld</SPAN> converts the =
packed BCD=20
integer into double extended precision floating-point format and pushes =
this=20
value onto the FPU stack. <SPAN class=3Dsmallcode>fbstp</SPAN> converts =
the value=20
in ST0 to an 18-digit packed BCD integer, stores the result in the =
destination=20
operand, and pops the register stack. The operand should be an 80-bit =
memory=20
location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fadd</SPAN> adds the =
destination and=20
source operand and stores the sum in the destination location. The =
destination=20
operand is always an FPU register, if the source is a memory location, =
the=20
destination is ST0 register and only source operand should be specified. =
If both=20
operands are FPU registers, at least one of them should be ST0 register. =
An=20
operand in memory can be a 32-bit or 64-bit value. </P><PRE =
class=3Dsmallcode>    fadd qword [bx]  ; add double precision value to =
st0
    fadd st2,st0     ; add st0 to st2
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>faddp</SPAN> adds the =
destination and=20
source operand, stores the sum in the destination location and then pops =
the=20
register stack. The destination operand must be an FPU register and the =
source=20
operand must be the ST0. When no operands are specified, ST1 is used as =
a=20
destination operand. </P><PRE class=3Dsmallcode>    faddp            ; =
add st0 to st1 and pop the stack
    faddp st2,st0    ; add st0 to st2 and pop the stack
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fiadd</SPAN> instruction =
converts an=20
integer source operand into double extended precision floating-point =
value and=20
adds it to the destination operand. The operand should be a 16-bit or =
32-bit=20
memory location. </P><PRE class=3Dsmallcode>    fiadd word [bx]  ; add =
word integer to st0
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fsub</SPAN>, <SPAN=20
class=3Dsmallcode>fsubr</SPAN>, <SPAN class=3Dsmallcode>fmul</SPAN>, =
<SPAN=20
class=3Dsmallcode>fdiv</SPAN>, <SPAN class=3Dsmallcode>fdivr</SPAN> =
instruction are=20
similar to <SPAN class=3Dsmallcode>fadd</SPAN>, have the same rules for =
operands=20
and differ only in the perfomed computation. <SPAN =
class=3Dsmallcode>fsub</SPAN>=20
substracts the source operand from the destination operand, <SPAN=20
class=3Dsmallcode>fsubr</SPAN> substract the destination operand from =
the source=20
operand, <SPAN class=3Dsmallcode>fmul</SPAN> multiplies the destination =
and source=20
operands, <SPAN class=3Dsmallcode>fdiv</SPAN> divides the destination =
operand by=20
the source operand and <SPAN class=3Dsmallcode>fdivr</SPAN> divides the =
source=20
operand by the destination operand. <SPAN =
class=3Dsmallcode>fsubp</SPAN>, <SPAN=20
class=3Dsmallcode>fsubrp</SPAN>, <SPAN class=3Dsmallcode>fmulp</SPAN>, =
<SPAN=20
class=3Dsmallcode>fdivp</SPAN>, <SPAN class=3Dsmallcode>fdivrp</SPAN> =
perform the=20
same operations and pop the register stack, the rules for operand are =
the same=20
as for the <SPAN class=3Dsmallcode>faddp</SPAN> instruction. <SPAN=20
class=3Dsmallcode>fisub</SPAN>, <SPAN class=3Dsmallcode>fisubr</SPAN>, =
<SPAN=20
class=3Dsmallcode>fimul</SPAN>, <SPAN class=3Dsmallcode>fidiv</SPAN>, =
<SPAN=20
class=3Dsmallcode>fidivr</SPAN> perform these operations after =
converting the=20
integer source operand into floating-point value, they have the same =
rules for=20
operands as <SPAN class=3Dsmallcode>fiadd</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fsqrt</SPAN> computes the =
square root=20
of the value in ST0 register, <SPAN class=3Dsmallcode>fsin</SPAN> =
computes the=20
sine of that value, <SPAN class=3Dsmallcode>fcos</SPAN> computes the =
cosine of=20
that value, <SPAN class=3Dsmallcode>fchs</SPAN> complements its sign =
bit, <SPAN=20
class=3Dsmallcode>fabs</SPAN> clears its sign to create the absolute =
value, <SPAN=20
class=3Dsmallcode>frndint</SPAN> rounds it to the nearest integral =
value,=20
depending on the current rounding mode. <SPAN =
class=3Dsmallcode>f2xm1</SPAN>=20
computes the exponential value of 2 to the power of ST0 and substracts =
the 1.0=20
from it, the value of ST0 must lie in the range -1.0 to +1.0. All these=20
instructions store the result in ST0 and have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fsincos</SPAN> computes =
both the sine=20
and the cosine of the value in ST0 register, stores the sine in ST0 and =
pushes=20
the cosine on the top of FPU register stack. <SPAN =
class=3Dsmallcode>fptan</SPAN>=20
computes the tangent of the value in ST0, stores the result in ST0 and =
pushes a=20
1.0 onto the FPU register stack. <SPAN class=3Dsmallcode>fpatan</SPAN> =
computes=20
the arctangent of the value in ST1 divided by the value in ST0, stores =
the=20
result in ST1 and pops the FPU register stack. <SPAN=20
class=3Dsmallcode>fyl2x</SPAN> computes the binary logarithm of ST0, =
multiplies it=20
by ST1, stores the result in ST1 and pop the FPU register stack; <SPAN=20
class=3Dsmallcode>fyl2xp1</SPAN> performs the same operation but it adds =
1.0 to=20
ST0 before computing the logarithm. <SPAN class=3Dsmallcode>fprem</SPAN> =
computes=20
the remainder obtained from dividing the value in ST0 by the value in =
ST1, and=20
stores the result in ST0. <SPAN class=3Dsmallcode>fprem1</SPAN> performs =
the same=20
operation as <SPAN class=3Dsmallcode>fprem</SPAN>, but it computes the =
remainder=20
in the way specified by IEEE Standard 754. <SPAN =
class=3Dsmallcode>fscale</SPAN>=20
truncates the value in ST1 and increases the exponent of ST0 by this =
value.=20
<SPAN class=3Dsmallcode>fxtract</SPAN> separates the value in ST0 into =
its=20
exponent and significand, stores the exponent in ST0 and pushes the =
significand=20
onto the register stack. <SPAN class=3Dsmallcode>fnop</SPAN> performs no =

operation. These instructions have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fxch</SPAN> exchanges the =
contents of=20
ST0 an another FPU register. The operand should be an FPU register, if =
no=20
operand is specified, the contents of ST0 and ST1 are exchanged. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fcom</SPAN> and <SPAN=20
class=3Dsmallcode>fcomp</SPAN> compare the contents of ST0 and the =
source operand=20
and set flags in the FPU status word according to the results. <SPAN=20
class=3Dsmallcode>fcomp</SPAN> additionally pops the register stack =
after=20
performing the comparision. The operand can be a single or double =
precision=20
value in memory or the FPU register. When no operand is specified, ST1 =
is used=20
as a source operand. </P><PRE class=3Dsmallcode>    fcom             ; =
compare st0 with st1
    fcomp st2        ; compare st0 with st2 and pop stack
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fcompp</SPAN> compares the =
contents of=20
ST0 and ST1, sets flags in the FPU status word according to the results =
and pops=20
the register stack twice. This instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fucom</SPAN>, <SPAN=20
class=3Dsmallcode>fucomp</SPAN> and <SPAN =
class=3Dsmallcode>fucompp</SPAN> performs=20
an unordered comparision of two FPU registers. Rules for operands are =
the same=20
as for the <SPAN class=3Dsmallcode>fcom</SPAN>, <SPAN =
class=3Dsmallcode>fcomp</SPAN>=20
and <SPAN class=3Dsmallcode>fcompp</SPAN>, but the source operand must =
be an FPU=20
register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ficom</SPAN> and <SPAN=20
class=3Dsmallcode>ficomp</SPAN> compare the value in ST0 with an integer =
source=20
operand and set the flags in the FPU status word according to the =
results. <SPAN=20
class=3Dsmallcode>ficomp</SPAN> additionally pops the register stack =
after=20
performing the comparision. The integer value is converted to double =
extended=20
precision floating-point format before the comparision is made. The =
operand=20
should be a 16-bit or 32-bit memory location. </P><PRE =
class=3Dsmallcode>    ficom word [bx]  ; compare st0 with 16-bit integer
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fcomi</SPAN>, <SPAN=20
class=3Dsmallcode>fcomip</SPAN>, <SPAN class=3Dsmallcode>fucomi</SPAN>, =
<SPAN=20
class=3Dsmallcode>fucomip</SPAN> perform the comparision of ST0 with =
another FPU=20
register and set the ZF, PF and CF flags according to the results. <SPAN =

class=3Dsmallcode>fcomip</SPAN> and <SPAN =
class=3Dsmallcode>fucomip</SPAN>=20
additionaly pop the register stack after performing the comparision. The =

instructions obtained by attaching the FPU condition mnemonic (see table =
<A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.2">2.2</A>)=
 to the=20
<SPAN class=3Dsmallcode>fcmov</SPAN> mnemonic transfer the specified FPU =
register=20
into ST0 register if the given test condition is true. These =
instructions allow=20
two different syntaxes, one with single operand specifying the source =
FPU=20
register, and one with two operands, in that case destination operand =
should be=20
ST0 register and the second operand specifies the source FPU register. =
</P><PRE class=3Dsmallcode>    fcomi st2        ; compare st0 with st2 =
and set flags
    fcmovb st0,st2   ; transfer st2 to st0 if below
</PRE>
<P class=3Dsmalltext><B><A name=3D_2.2>Table 2.2 FPU conditions</A></B> =
</P>
<TABLE style=3D"WIDTH: 350px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Mnemonic</TH>
    <TH>Condition tested</TH>
    <TH>Description</TH></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>b</SPAN></TD>
    <TD>CF =3D 1</TD>
    <TD>below</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>e</SPAN></TD>
    <TD>ZF =3D 1</TD>
    <TD>equal</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>be</SPAN></TD>
    <TD>CF <SPAN class=3Dsmallcode>or</SPAN> ZF =3D 1</TD>
    <TD>equal</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>u</SPAN></TD>
    <TD>PF =3D 1</TD>
    <TD>unordered</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>nb</SPAN></TD>
    <TD>CF =3D 0</TD>
    <TD>not below</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>ne</SPAN></TD>
    <TD>ZF =3D 0</TD>
    <TD>not equal</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>nbe</SPAN></TD>
    <TD>CF <SPAN class=3Dsmallcode>or</SPAN> ZF =3D 0</TD>
    <TD>not equal</TD></TR>
  <TR>
    <TD><SPAN class=3Dsmallcode>nu</SPAN></TD>
    <TD>PF =3D 0</TD>
    <TD>not unordered</TD></TR></TBODY></TABLE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ftst</SPAN> compares the =
value in ST0=20
with 0.0 and sets the flags in the FPU status word according to the =
results.=20
<SPAN class=3Dsmallcode>fxam</SPAN> examines the contents of the ST0 and =
sets the=20
flags in FPU status word to indicate the class of value in the register. =
These=20
instructions have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fstsw</SPAN> and <SPAN=20
class=3Dsmallcode>fnstsw</SPAN> store the current value of the FPU =
status word in=20
the destination location. The destination operand can be either a 16-bit =
memory=20
or the AX register. <SPAN class=3Dsmallcode>fstsw</SPAN> checks for =
pending=20
unmasked FPU exceptions before storing the status word, <SPAN=20
class=3Dsmallcode>fnstsw</SPAN> does not. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fstcw</SPAN> and <SPAN=20
class=3Dsmallcode>fnstcw</SPAN> store the current value of the FPU =
control word at=20
the specified destination in memory. <SPAN =
class=3Dsmallcode>fstcw</SPAN> checks=20
for pending umasked FPU exceptions before storing the control word, =
<SPAN=20
class=3Dsmallcode>fnstcw</SPAN> does not. <SPAN =
class=3Dsmallcode>fldcw</SPAN> loads=20
the operand into the FPU control word. The operand should be a 16-bit =
memory=20
location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fstenv</SPAN> and <SPAN=20
class=3Dsmallcode>fnstenv</SPAN> store the current FPU operating =
environment at=20
the memory location specified with the destination operand, and then =
mask all=20
FPU exceptions. <SPAN class=3Dsmallcode>fstenv</SPAN> checks for pending =
umasked=20
FPU exceptions before proceeding, <SPAN class=3Dsmallcode>fnstenv</SPAN> =
does not.=20
<SPAN class=3Dsmallcode>fldenv</SPAN> loads the complete operating =
environment=20
from memory into the FPU. <SPAN class=3Dsmallcode>fsave</SPAN> and <SPAN =

class=3Dsmallcode>fnsave</SPAN> store the current FPU state (operating =
environment=20
and register stack) at the specified destination in memory and =
reinitializes the=20
FPU. <SPAN class=3Dsmallcode>fsave</SPAN> check for pending unmasked FPU =

exceptions before proceeding, <SPAN class=3Dsmallcode>fnsave</SPAN> does =
not.=20
<SPAN class=3Dsmallcode>frstor</SPAN> loads the FPU state from the =
specified=20
memory location. All these instructions need an operand being a memory =
location.=20
For each of these instructions exist two additional mnemonics that allow =
to=20
precisely select the type of the operation. The <SPAN=20
class=3Dsmallcode>fstenvw</SPAN>, <SPAN =
class=3Dsmallcode>fnstenvw</SPAN>, <SPAN=20
class=3Dsmallcode>fldenvw</SPAN>, <SPAN class=3Dsmallcode>fsavew</SPAN>, =
<SPAN=20
class=3Dsmallcode>fnsavew</SPAN> and <SPAN =
class=3Dsmallcode>frstorw</SPAN>=20
mnemonics force the instruction to perform operation as in the 16-bit =
mode,=20
while <SPAN class=3Dsmallcode>fstenvd</SPAN>, <SPAN=20
class=3Dsmallcode>fnstenvd</SPAN>, <SPAN =
class=3Dsmallcode>fldenvd</SPAN>, <SPAN=20
class=3Dsmallcode>fsaved</SPAN>, <SPAN class=3Dsmallcode>fnsaved</SPAN> =
and <SPAN=20
class=3Dsmallcode>frstord</SPAN> force the operation as in 32-bit mode. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>finit</SPAN> and <SPAN=20
class=3Dsmallcode>fninit</SPAN> set the FPU operating environment into =
its default=20
state. <SPAN class=3Dsmallcode>finit</SPAN> checks for pending unmasked =
FPU=20
exception before proceeding, <SPAN class=3Dsmallcode>fninit</SPAN> does =
not. <SPAN=20
class=3Dsmallcode>fclex</SPAN> and <SPAN class=3Dsmallcode>fnclex</SPAN> =
clear the=20
FPU exception flags in the FPU status word. <SPAN =
class=3Dsmallcode>fclex</SPAN>=20
checks for pending unmasked FPU exception before proceeding, <SPAN=20
class=3Dsmallcode>fnclex</SPAN> does not. <SPAN =
class=3Dsmallcode>wait</SPAN> and=20
<SPAN class=3Dsmallcode>fwait</SPAN> are synonyms for the same =
instruction, which=20
causes the processor to check for pending unmasked FPU exceptions and =
handle=20
them before proceeding. These instructions have no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ffree</SPAN> sets the tag =
associated=20
with specified FPU register to empty. The operand should be an FPU =
register.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fincstp</SPAN> and <SPAN=20
class=3Dsmallcode>fdecstp</SPAN> rotate the FPU stack by one by adding =
or=20
substracting one to the pointer of the top of stack. These instructions =
have no=20
operands. </P>
<P><B><A class=3Dsmalltext name=3D2.1.14>2.1.14 MMX instructions</A> =
</B></P>
<P class=3Dsmalltext>The MMX instructions operate on the packed integer =
types and=20
use the MMX registers, which are the low 64-bit parts of the 80-bit FPU=20
registers. Because of this MMX instructions cannot be used at the same =
time as=20
FPU instructions. They can operate on packed bytes (eight 8-bit =
integers),=20
packed words (four 16-bit integers) or packed double words (two 32-bit=20
integers), use of packed formats allows to perform operations on =
multiple data=20
at one time. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movq</SPAN> copies a quad =
word from the=20
source operand to the destination operand. At least one of the operands =
must be=20
a MMX register, the second one can be also a MMX register or 64-bit =
memory=20
location. </P><PRE class=3Dsmallcode>    movq mm0,mm1     ; move quad =
word from register to register
    movq mm2,[ebx]   ; move quad word from memory to register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movd</SPAN> copies a double =
word from=20
the source operand to the destination operand. One of the operands must =
be a MMX=20
register, the second one can be a general register or 32-bit memory =
location.=20
Only low double word of MMX register is used. </P>
<P class=3Dsmalltext>All general MMX operations have two operands, the =
destination=20
operand should be a MMX register, the source operand can be a MMX =
register or=20
64-bit memory location. Operation is performed on the corresponding data =

elements of the source and destination operand and stored in the data =
elements=20
of the destination operand. <SPAN class=3Dsmallcode>paddb</SPAN>, <SPAN=20
class=3Dsmallcode>paddw</SPAN> and <SPAN class=3Dsmallcode>paddd</SPAN> =
perform the=20
addition of packed bytes, packed words, or packed double words. <SPAN=20
class=3Dsmallcode>psubb</SPAN>, <SPAN class=3Dsmallcode>psubw</SPAN> and =
<SPAN=20
class=3Dsmallcode>psubd</SPAN> perform the substraction of appropriate =
types.=20
<SPAN class=3Dsmallcode>paddsb</SPAN>, <SPAN =
class=3Dsmallcode>paddsw</SPAN>, <SPAN=20
class=3Dsmallcode>psubsb</SPAN> and <SPAN =
class=3Dsmallcode>psubsw</SPAN> perform=20
the addition or substraction of packed bytes or packed words with the =
signed=20
saturation. <SPAN class=3Dsmallcode>paddusb</SPAN>, <SPAN=20
class=3Dsmallcode>paddusw</SPAN>, <SPAN =
class=3Dsmallcode>psubusb</SPAN>, <SPAN=20
class=3Dsmallcode>psubusw</SPAN> are analoguous, but with unsigned =
saturation.=20
<SPAN class=3Dsmallcode>pmulhw</SPAN> and <SPAN =
class=3Dsmallcode>pmullw</SPAN>=20
performs a signed multiplication of the packed words and store the high =
or low=20
words of the results in the destination operand. <SPAN=20
class=3Dsmallcode>pmaddwd</SPAN> performs a multiply of the packed words =
and adds=20
the four intermediate double word products in pairs to produce result as =
a=20
packed double words. <SPAN class=3Dsmallcode>pand</SPAN>, <SPAN=20
class=3Dsmallcode>por</SPAN> and <SPAN class=3Dsmallcode>pxor</SPAN> =
perform the=20
logical operations on the quad words, <SPAN =
class=3Dsmallcode>pandn</SPAN> peforms=20
also a logical negation of the destination operand before performing the =
<SPAN=20
class=3Dsmallcode>and</SPAN> operation. <SPAN =
class=3Dsmallcode>pcmpeqb</SPAN>,=20
<SPAN class=3Dsmallcode>pcmpeqw</SPAN> and <SPAN =
class=3Dsmallcode>pcmpeqd</SPAN>=20
compare for equality of packed bytes, packed words or packed double =
words. If a=20
pair of data elements is equal, the corresponding data element in the=20
destination operand is filled with bits of value 1, otherwise it's set =
to 0.=20
<SPAN class=3Dsmallcode>pcmpgtb</SPAN>, <SPAN =
class=3Dsmallcode>pcmpgtw</SPAN> and=20
<SPAN class=3Dsmallcode>pcmpgtd</SPAN> perform the similar operation, =
but they=20
check whether the data elements in the destination operand are greater =
than the=20
correspoding data elements in the source operand. <SPAN=20
class=3Dsmallcode>packsswb</SPAN> converts packed signed words into =
packed signed=20
bytes, <SPAN class=3Dsmallcode>packssdw</SPAN> converts packed signed =
double words=20
into packed signed words, using saturation to handle overflow =
conditions. <SPAN=20
class=3Dsmallcode>packuswb</SPAN> converts packed signed words into =
packed=20
unsigned bytes. Converted data elements from the source operand are =
stored in=20
the low part of the destination operand, while converted data elements =
from the=20
destination operand are stored in the high part. <SPAN=20
class=3Dsmallcode>punpckhbw</SPAN>, <SPAN =
class=3Dsmallcode>punpckhwd</SPAN> and=20
<SPAN class=3Dsmallcode>punpckhdq</SPAN> interleaves the data elements =
from the=20
high parts of the source and destination operands and stores the result =
into the=20
destination operand. <SPAN class=3Dsmallcode>punpcklbw</SPAN>, <SPAN=20
class=3Dsmallcode>punpcklwd</SPAN> and <SPAN =
class=3Dsmallcode>punpckldq</SPAN>=20
perform the same operation, but the low parts of the source and =
destination=20
operand are used. </P><PRE class=3Dsmallcode>    paddsb mm0,[esi] ; add =
packed bytes with signed saturation
    pcmpeqw mm3,mm7  ; compare packed words for equality
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>psllw</SPAN>, <SPAN=20
class=3Dsmallcode>pslld</SPAN> and <SPAN class=3Dsmallcode>psllq</SPAN> =
perform=20
logical shift left of the packed words, packed double words or a single =
quad=20
word in the destination operand by the amount specified in the source =
operand.=20
<SPAN class=3Dsmallcode>psrlw</SPAN>, <SPAN =
class=3Dsmallcode>psrld</SPAN> and <SPAN=20
class=3Dsmallcode>psrlq</SPAN> perform logical shift right of the packed =
words,=20
packed double words or a single quad word. <SPAN =
class=3Dsmallcode>psraw</SPAN>=20
and <SPAN class=3Dsmallcode>psrad</SPAN> perform arithmetic shift of the =
packed=20
words or double words. The destination operand should be a MMX register, =
while=20
source operand can be a MMX register, 64-bit memory location, or 8-bit =
immediate=20
value. </P><PRE class=3Dsmallcode>    psllw mm2,mm4    ; shift words =
left logically
    psrad mm4,[ebx]  ; shift double words right arithmetically
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>emms</SPAN> makes the FPU =
registers=20
usable for the FPU instructions, it must be used before using the FPU=20
instructions if any MMX instructions were used. </P>
<P><B><A class=3Dsmalltext name=3D2.1.15>2.1.15 SSE instructions</A> =
</B></P>
<P class=3Dsmalltext>The SSE extension adds more MMX instructions and =
also=20
introduces the operations on packed single precision floating point =
values. The=20
128-bit packed single precision format consists of four single precision =

floating point values. The 128-bit SSE registers are designed for the =
purpose of=20
operations on this data type. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movaps</SPAN> and <SPAN=20
class=3Dsmallcode>movups</SPAN> transfer a double quad word operand =
containing=20
packed single precision values from source operand to destination =
operand. At=20
least one of the operands have to be a SSE register, the second one can =
be also=20
a SSE register or 128-bit memory location. Memory operands for <SPAN=20
class=3Dsmallcode>movaps</SPAN> instruction must be aligned on boundary =
of 16=20
bytes, operands for <SPAN class=3Dsmallcode>movups</SPAN> instruction =
don't have=20
to be aligned. </P><PRE class=3Dsmallcode>    movups xmm0,[ebx]  ; move =
unaligned double quad word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movlps</SPAN> moves packed =
two single=20
precision values between the memory and the low quad word of SSE =
register. <SPAN=20
class=3Dsmallcode>movhps</SPAN> moved packed two single precision values =
between=20
the memory and the high quad word of SSE register. One of the operands =
must be a=20
SSE register, and the other operand must be a 64-bit memory location. =
</P><PRE class=3Dsmallcode>    movlps xmm0,[ebx]  ; move memory to low =
quad word of xmm0
    movhps [esi],xmm7  ; move high quad word of xmm7 to memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movlhps</SPAN> moves packed =
two single=20
precision values from the low quad word of source register to the high =
quad word=20
of destination register. <SPAN class=3Dsmallcode>movhlps</SPAN> moves =
two packed=20
single precision values from the high quad word of source register to =
the low=20
quad word of destination register. Both operands have to be a SSE =
registers.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movmskps</SPAN> transfers =
the most=20
significant bit of each of the four single precision values in the SSE =
register=20
into low four bits of a general register. The source operand must be a =
SSE=20
register, the destination operand must be a general register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movss</SPAN> transfers a =
single=20
precision value between source and destination operand (only the low =
double word=20
is trasferred). At least one of the operands have to be a SSE register, =
the=20
second one can be also a SSE register or 32-bit memory location. =
</P><PRE class=3Dsmallcode>    movss [edi],xmm3   ; move low double word =
of xmm3 to memory
</PRE>
<P class=3Dsmalltext>Each of the SSE arithmetic operations has two =
variants. When=20
the mnemonic ends with <SPAN class=3Dsmallcode>ps</SPAN>, the source =
operand can=20
be a 128-bit memory location or a SSE register, the destination operand =
must be=20
a SSE register and the operation is performed on packed four single =
precision=20
values, for each pair of the corresponding data elements separately, the =
result=20
is stored in the destination register. When the mnemonic ends with <SPAN =

class=3Dsmallcode>ss</SPAN>, the source operand can be a 32-bit memory =
location or=20
a SSE register, the destination operand must be a SSE register and the =
operation=20
is performed on single precision values, only low double words of SSE =
registers=20
are used in this case, the result is stored in the low double word of=20
destination register. <SPAN class=3Dsmallcode>addps</SPAN> and <SPAN=20
class=3Dsmallcode>addss</SPAN> add the values, <SPAN =
class=3Dsmallcode>subps</SPAN>=20
and <SPAN class=3Dsmallcode>subss</SPAN> substract the source value from =

destination value, <SPAN class=3Dsmallcode>mulps</SPAN> and <SPAN=20
class=3Dsmallcode>mulss</SPAN> multiply the values, <SPAN=20
class=3Dsmallcode>divps</SPAN> and <SPAN class=3Dsmallcode>divss</SPAN> =
divide the=20
destination value by the source value, <SPAN =
class=3Dsmallcode>rcpps</SPAN> and=20
<SPAN class=3Dsmallcode>rcpss</SPAN> compute the approximate reciprocal =
of the=20
source value, <SPAN class=3Dsmallcode>sqrtps</SPAN> and <SPAN=20
class=3Dsmallcode>sqrtss</SPAN> compute the square root of the source =
value, <SPAN=20
class=3Dsmallcode>rsqrtps</SPAN> and <SPAN =
class=3Dsmallcode>rsqrtss</SPAN> compute=20
the approximate reciprocal of square root of the source value, <SPAN=20
class=3Dsmallcode>maxps</SPAN> and <SPAN class=3Dsmallcode>maxss</SPAN> =
compare the=20
source and destination values and return the greater one, <SPAN=20
class=3Dsmallcode>minps</SPAN> and <SPAN class=3Dsmallcode>minss</SPAN> =
compare the=20
source and destination values and return the lesser one. </P><PRE =
class=3Dsmallcode>    mulss xmm0,[ebx]   ; multiply single precision =
values
    addps xmm3,xmm7    ; add packed single precision values
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>andps</SPAN>, <SPAN=20
class=3Dsmallcode>andnps</SPAN>, <SPAN class=3Dsmallcode>orps</SPAN> and =
<SPAN=20
class=3Dsmallcode>xorps</SPAN> perform the logical operations on packed =
single=20
precision values. The source operand can be a 128-bit memory location or =
a SSE=20
register, the destination operand must be a SSE register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmpps</SPAN> compares =
packed single=20
precision values and returns a mask result into the destination operand, =
which=20
must be a SSE register. The source operand can be a 128-bit memory =
location or=20
SSE register, the third operand must be an immediate operand selecting =
code of=20
one of the eight compare conditions (table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.3">2.3</A>)=
. <SPAN=20
class=3Dsmallcode>cmpss</SPAN> performs the same operation on single =
precision=20
values, only low double word of destination register is affected, in =
this case=20
source operand can be a 32-bit memory location or SSE register. These =
two=20
instructions have also variants with only two operands and the condition =
encoded=20
within mnemonic. Their mnemonics are obtained by attaching the mnemonic =
from=20
table <A =
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.3">2.3</A> =
to=20
the <SPAN class=3Dsmallcode>cmp</SPAN> mnemonic and then attaching the =
<SPAN=20
class=3Dsmallcode>ps</SPAN> or <SPAN class=3Dsmallcode>ss</SPAN> at the =
end. </P><PRE class=3Dsmallcode>    cmpps xmm2,xmm4,0  ; compare packed =
single precision values
    cmpltss xmm0,[ebx] ; compare single precision values
</PRE>
<P class=3Dsmalltext><B><A name=3D_2.3>Table 2.3 SSE conditions</A></B> =
</P>
<TABLE style=3D"WIDTH: 350px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Code</TH>
    <TH>Mnemonic</TH>
    <TH>Description</TH></TR>
  <TR>
    <TD>0</TD>
    <TD><SPAN class=3Dsmallcode>eq</SPAN></TD>
    <TD>equal</TD></TR>
  <TR>
    <TD>1</TD>
    <TD><SPAN class=3Dsmallcode>lt</SPAN></TD>
    <TD>less than</TD></TR>
  <TR>
    <TD>2</TD>
    <TD><SPAN class=3Dsmallcode>le</SPAN></TD>
    <TD>less than or equal</TD></TR>
  <TR>
    <TD>3</TD>
    <TD><SPAN class=3Dsmallcode>unord</SPAN></TD>
    <TD>unordered</TD></TR>
  <TR>
    <TD>4</TD>
    <TD><SPAN class=3Dsmallcode>neq</SPAN></TD>
    <TD>not equal</TD></TR>
  <TR>
    <TD>5</TD>
    <TD><SPAN class=3Dsmallcode>nlt</SPAN></TD>
    <TD>not less than</TD></TR>
  <TR>
    <TD>6</TD>
    <TD><SPAN class=3Dsmallcode>nle</SPAN></TD>
    <TD>not less than nor equal</TD></TR>
  <TR>
    <TD>7</TD>
    <TD><SPAN class=3Dsmallcode>ord</SPAN></TD>
    <TD>ordered</TD></TR></TBODY></TABLE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>comiss</SPAN> and <SPAN=20
class=3Dsmallcode>ucomiss</SPAN> compare the single precision values and =
set the=20
ZF, PF and CF flags to show the result. The destination operand must be =
a SSE=20
register, the source operand can be a 32-bit memory location or SSE =
register.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shufps</SPAN> moves any two =
of the four=20
single precision values from the destination operand into the low quad =
word of=20
the destination operand, and any two of the four values from the source =
operand=20
into the high quad word of the destination operand. The destination =
operand must=20
be a SSE register, the source operand can be a 128-bit memory location =
or SSE=20
register, the third operand must be an 8-bit immediate value selecting =
which=20
values will be moved into the destination operand. Bits 0 and 1 select =
the value=20
to be moved from destination operand to the low double word of the =
result, bits=20
2 and 3 select the value to be moved from the destination operand to the =
second=20
double word, bits 4 and 5 select the value to be moved from the source =
operand=20
to the third double word, and bits 6 and 7 select the value to be moved =
from the=20
source operand to the high double word of the result. </P><PRE =
class=3Dsmallcode>    shufps xmm0,xmm0,10010011b ; shuffle double words
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>unpckhps</SPAN> performs an =
interleaved=20
unpack of the values from the high parts of the source and destination =
operands=20
and stores the result in the destination operand, which must be a SSE =
register.=20
The source operand can be a 128-bit memory location or a SSE register. =
<SPAN=20
class=3Dsmallcode>unpcklps</SPAN> performs an interleaved unpack of the =
values=20
from the low parts of the source and destination operand and stores the =
result=20
in the destination operand, the rules for operands are the same. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtpi2ps</SPAN> converts =
packed two=20
double word integers into the the packed two single precision floating =
point=20
values and stores the result in the low quad word of the destination =
operand,=20
which should be a SSE register. The source operand can be a 64-bit =
memory=20
location or MMX register. </P><PRE class=3Dsmallcode>    cvtpi2ps =
xmm0,mm0  ; convert integers to single precision values
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtsi2ss</SPAN> converts a =
double word=20
integer into a single precision floating point value and stores the =
result in=20
the low double word of the destination operand, which should be a SSE =
register.=20
The source operand can be a 32-bit memory location or 32-bit general =
register.=20
</P><PRE class=3Dsmallcode>    cvtsi2ss xmm0,eax  ; convert integer to =
single precision value
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtps2pi</SPAN> converts =
packed two=20
single precision floating point values into packed two double word =
integers and=20
stores the result in the destination operand, which should be a MMX =
register.=20
The source operand can be a 64-bit memory location or SSE register, only =
low=20
quad word of SSE register is used. <SPAN =
class=3Dsmallcode>cvttps2pi</SPAN>=20
performs the similar operation, except that truncation is used to round =
a source=20
values to integers, rules for the operands are the same. </P><PRE =
class=3Dsmallcode>    cvtps2pi mm0,xmm0  ; convert single precision =
values to integers
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtss2si</SPAN> convert a =
single=20
precision floating point value into a double word integer and stores the =
result=20
in the destination operand, which should be a 32-bit general register. =
The=20
source operand can be a 32-bit memory location or SSE register, only low =
double=20
word of SSE register is used. <SPAN class=3Dsmallcode>cvttss2si</SPAN> =
performs=20
the similar operation, except that truncation is used to round a source =
value to=20
integer, rules for the operands are the same. </P><PRE =
class=3Dsmallcode>    cvtss2si eax,xmm0  ; convert single precision =
value to integer
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pextrw</SPAN> copies the =
word in the=20
source operand specified by the third operand to the destination =
operand. The=20
source operand must be a MMX register, the destination operand must be a =
32-bit=20
general register (the high word of the destination is cleared), the =
third=20
operand must an 8-bit immediate value. </P><PRE class=3Dsmallcode>    =
pextrw eax,mm0,1   ; extract word into eax
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pinsrw</SPAN> inserts a =
word from the=20
source operand in the destination operand at the location specified with =
the=20
third operand, which must be an 8-bit immediate value. The destination =
operand=20
must be a MMX register, the source operand can be a 16-bit memory =
location or=20
32-bit general register (only low word of the register is used). =
</P><PRE class=3Dsmallcode>    pinsrw mm1,ebx,2   ; insert word from ebx
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pavgb</SPAN> and <SPAN=20
class=3Dsmallcode>pavgw</SPAN> compute average of packed bytes or words. =
<SPAN=20
class=3Dsmallcode>pmaxub</SPAN> return the maximum values of packed =
unsigned=20
bytes, <SPAN class=3Dsmallcode>pminub</SPAN> returns the minimum values =
of packed=20
unsigned bytes, <SPAN class=3Dsmallcode>pmaxsw</SPAN> returns the =
maximum values=20
of packed signed words, <SPAN class=3Dsmallcode>pminsw</SPAN> returns =
the minimum=20
values of packed signed words. <SPAN class=3Dsmallcode>pmulhuw</SPAN> =
performs a=20
unsigned multiplication of the packed words and stores the high words of =
the=20
results in the destination operand. <SPAN =
class=3Dsmallcode>psadbw</SPAN> computes=20
the absolute differences of packed unsigned bytes, sums the differences, =
and=20
stores the sum in the low word of destination operand. All these =
instructions=20
follow the same rules for operands as the general MMX operations =
described in=20
previous section. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pmovmskb</SPAN> creates a =
mask made of=20
the most significant bit of each byte in the source operand and stores =
the=20
result in the low byte of destination operand. The source operand must =
be a MMX=20
register, the destination operand must a 32-bit general register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pshufw</SPAN> inserts words =
from the=20
source operand in the destination operand from the locations specified =
with the=20
third operand. The destination operand must be a MMX register, the =
source=20
operand can be a 64-bit memory location or MMX register, third operand =
must an=20
8-bit immediate value selecting which values will be moved into =
destination=20
operand, in the similar way as the third operand of the <SPAN=20
class=3Dsmallcode>shufps</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movntq</SPAN> moves the =
quad word from=20
the source operand to memory using a non-temporal hint to minimize cache =

pollution. The source operand should be a MMX register, the destination =
operand=20
should be a 64-bit memory location. <SPAN =
class=3Dsmallcode>movntps</SPAN> stores=20
packed single precision values from the SSE register to memory using a=20
non-temporal hint. The source operand should be a SSE register, the =
destination=20
operand should be a 128-bit memory location. <SPAN=20
class=3Dsmallcode>maskmovq</SPAN> stores selected bytes from the first =
operand=20
into a 64-bit memory location using a non-temporal hint. Both operands =
should be=20
a MMX registers, the second operand selects wich bytes from the source =
operand=20
are written to memory. The memory location is pointed by DI (or EDI) =
register in=20
the segment selected by DS. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>prefetcht0</SPAN>, <SPAN=20
class=3Dsmallcode>prefetcht1</SPAN>, <SPAN =
class=3Dsmallcode>prefetcht2</SPAN> and=20
<SPAN class=3Dsmallcode>prefetchnta</SPAN> fetch the line of data from =
memory that=20
contains byte specified with the operand to a specified location in =
hierarchy.=20
The operand should be an 8-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>sfence</SPAN> performs a =
serializing=20
operation on all instruction storing to memory that were issued prior to =
it.=20
This instruction has no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ldmxcsr</SPAN> loads the =
32-bit memory=20
operand into the MXCSR register. <SPAN class=3Dsmallcode>stmxcsr</SPAN> =
stores the=20
contents of MXCSR into a 32-bit memory operand. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fxsave</SPAN> saves the =
current state=20
of the FPU, MXCSR register, and all the FPU and SSE registers to a =
512-byte=20
memory location specified in the destination operand. <SPAN=20
class=3Dsmallcode>fxrstor</SPAN> reloads data previously stored with =
<SPAN=20
class=3Dsmallcode>fxsave</SPAN> instruction from the specified 512-byte =
memory=20
location. The memory operand for both those instructions must be aligned =
on 16=20
byte boundary, it should declare operand of no specified size. </P>
<P><B><A class=3Dsmalltext name=3D2.1.16>2.1.16 SSE2 instructions</A> =
</B></P>
<P class=3Dsmalltext>The SSE2 extension introduces the operations on =
packed double=20
precision floating point values, extends the syntax of MMX instructions, =
and=20
adds also some new instructions. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movapd</SPAN> and <SPAN=20
class=3Dsmallcode>movupd</SPAN> transfer a double quad word operand =
containing=20
packed double precision values from source operand to destination =
operand. These=20
instructions are analogous to <SPAN class=3Dsmallcode>movaps</SPAN> and =
<SPAN=20
class=3Dsmallcode>movups</SPAN> and have the same rules for operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movlpd</SPAN> moves double =
precision=20
value between the memory and the low quad word of SSE register. <SPAN=20
class=3Dsmallcode>movhpd</SPAN> moved double precision value between the =
memory=20
and the high quad word of SSE register. These instructions are analogous =
to=20
<SPAN class=3Dsmallcode>movlps</SPAN> and <SPAN =
class=3Dsmallcode>movhps</SPAN> and=20
have the same rules for operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movmskpd</SPAN> transfers =
the most=20
significant bit of each of the two double precision values in the SSE =
register=20
into low two bits of a general register. This instruction is analogous =
to <SPAN=20
class=3Dsmallcode>movmskps</SPAN> and has the same rules for operands. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movsd</SPAN> transfers a =
double=20
precision value between source and destination operand (only the low =
quad word=20
is trasferred). At least one of the operands have to be a SSE register, =
the=20
second one can be also a SSE register or 64-bit memory location. </P>
<P class=3Dsmalltext>Arithmetic operations on double precision values =
are: <SPAN=20
class=3Dsmallcode>addpd</SPAN>, <SPAN class=3Dsmallcode>addsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>subpd</SPAN>, <SPAN class=3Dsmallcode>subsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>mulpd</SPAN>, <SPAN class=3Dsmallcode>mulsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>divpd</SPAN>, <SPAN class=3Dsmallcode>divsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>sqrtpd</SPAN>, <SPAN class=3Dsmallcode>sqrtsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>maxpd</SPAN>, <SPAN class=3Dsmallcode>maxsd</SPAN>, =
<SPAN=20
class=3Dsmallcode>minpd</SPAN>, <SPAN class=3Dsmallcode>minsd</SPAN>, =
and they are=20
analoguous to arithmetic operations on single precision values described =
in=20
previous section. When the mnemonic ends with <SPAN =
class=3Dsmallcode>pd</SPAN>=20
instead of <SPAN class=3Dsmallcode>ps</SPAN>, the operation is performed =
on packed=20
two double precision values, but rules for operands are the same. When =
the=20
mnemonic ends with <SPAN class=3Dsmallcode>sd</SPAN> instead of <SPAN=20
class=3Dsmallcode>ss</SPAN>, the source operand can be a 64-bit memory =
location or=20
a SSE register, the destination operand must be a SSE register and the =
operation=20
is performed on double precision values, only low quad words of SSE =
registers=20
are used in this case. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>andpd</SPAN>, <SPAN=20
class=3Dsmallcode>andnpd</SPAN>, <SPAN class=3Dsmallcode>orpd</SPAN> and =
<SPAN=20
class=3Dsmallcode>xorpd</SPAN> perform the logical operations on packed =
double=20
precision values. They are analoguous to SSE logical operations on =
single=20
prevision values and have the same rules for operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cmppd</SPAN> compares =
packed double=20
precision values and returns and returns a mask result into the =
destination=20
operand. This instruction is analoguous to <SPAN =
class=3Dsmallcode>cmpps</SPAN>=20
and has the same rules for operands. <SPAN =
class=3Dsmallcode>cmpsd</SPAN> performs=20
the same operation on double precision values, only low quad word of =
destination=20
register is affected, in this case source operand can be a 64-bit memory =
or SSE=20
register. Variant with only two operands are obtained by attaching the =
condition=20
mnemonic from table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.3">2.3</A> =
to the=20
<SPAN class=3Dsmallcode>cmp</SPAN> mnemonic and then attaching the <SPAN =

class=3Dsmallcode>pd</SPAN> or <SPAN class=3Dsmallcode>sd</SPAN> at the =
end. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>comisd</SPAN> and <SPAN=20
class=3Dsmallcode>ucomisd</SPAN> compare the double precision values and =
set the=20
ZF, PF and CF flags to show the result. The destination operand must be =
a SSE=20
register, the source operand can be a 128-bit memory location or SSE =
register.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shufpd</SPAN> moves any of =
the two=20
double precision values from the destination operand into the low quad =
word of=20
the destination operand, and any of the two values from the source =
operand into=20
the high quad word of the destination operand. This instruction is =
analoguous to=20
<SPAN class=3Dsmallcode>shufps</SPAN> and has the same rules for =
operand. Bit 0 of=20
the third operand selects the value to be moved from the destination =
operand,=20
bit 1 selects the value to be moved from the source operand, the rest of =
bits=20
are reserved and must be zeroed. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>unpckhpd</SPAN> performs an =
unpack of=20
the high quad words from the source and destination operands, <SPAN=20
class=3Dsmallcode>unpcklpd</SPAN> performs an unpack of the low quad =
words from=20
the source and destination operands. They are analoguous to <SPAN=20
class=3Dsmallcode>unpckhps</SPAN> and <SPAN =
class=3Dsmallcode>unpcklps</SPAN>, and=20
have the same rules for operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtps2pd</SPAN> converts =
the packed two=20
single precision floating point values to two packed double precision =
floating=20
point values, the destination operand must be a SSE register, the source =
operand=20
can be a 64-bit memory location or SSE register. <SPAN=20
class=3Dsmallcode>cvtpd2ps</SPAN> converts the packed two double =
precision=20
floating point values to packed two single precision floating point =
values, the=20
destination operand must be a SSE register, the source operand can be a =
128-bit=20
memory location or SSE register. <SPAN class=3Dsmallcode>cvtss2sd</SPAN> =
converts=20
the single precision floating point value to double precision floating =
point=20
value, the destination operand must be a SSE register, the source =
operand can be=20
a 32-bit memory location or SSE register. <SPAN =
class=3Dsmallcode>cvtsd2ss</SPAN>=20
converts the double precision floating point value to single precision =
floating=20
point value, the destination operand must be a SSE register, the source =
operand=20
can be 64-bit memory location or SSE register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtpi2pd</SPAN> converts =
packed two=20
double word integers into the the packed double precision floating point =
values,=20
the destination operand must be a SSE register, the source operand can =
be a=20
64-bit memory location or MMX register. <SPAN =
class=3Dsmallcode>cvtsi2sd</SPAN>=20
converts a double word integer into a double precision floating point =
value, the=20
destination operand must be a SSE register, the source operand can be a =
32-bit=20
memory location or 32-bit general register. <SPAN=20
class=3Dsmallcode>cvtpd2pi</SPAN> converts packed double precision =
floating point=20
values into packed two double word integers, the destination operand =
should be a=20
MMX register, the source operand can be a 128-bit memory location or SSE =

register. <SPAN class=3Dsmallcode>cvttpd2pi</SPAN> performs the similar =
operation,=20
except that truncation is used to round a source values to integers, =
rules for=20
operands are the same. <SPAN class=3Dsmallcode>cvtsd2si</SPAN> converts =
a double=20
precision floating point value into a double word integer, the =
destination=20
operand should be a 32-bit general register, the source operand can be a =
64-bit=20
memory location or SSE register. <SPAN =
class=3Dsmallcode>cvttsd2si</SPAN> performs=20
the similar operation, except that truncation is used to round a source =
value to=20
integer, rules for operands are the same. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>cvtps2dq</SPAN> and <SPAN=20
class=3Dsmallcode>cvttps2dq</SPAN> convert packed single precision =
floating point=20
values to packed four double word integers, storing them in the =
destination=20
operand. <SPAN class=3Dsmallcode>cvtpd2dq</SPAN> and <SPAN=20
class=3Dsmallcode>cvttpd2dq</SPAN> convert packed double precision =
floating point=20
values to packed two double word integers, storing the result in the low =
quad=20
word of the destination operand. <SPAN class=3Dsmallcode>cvtdq2ps</SPAN> =
converts=20
packed four double word integers to packed single precision floating =
point=20
values. For all these instructions destination operand must be a SSE =
register,=20
the source operand can be a 128-bit memory location or SSE register. =
<SPAN=20
class=3Dsmallcode>cvtdq2pd</SPAN> converts packed two double word =
integers from=20
the low quad word of the source operand to packed double precision =
floating=20
point values, the source can be a 64-bit memory location or SSE =
register,=20
destination has to be SSE register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movdqa</SPAN> and <SPAN=20
class=3Dsmallcode>movdqu</SPAN> transfer a double quad word operand =
containing=20
packed integers from source operand to destination operand. At least one =
of the=20
operands have to be a SSE register, the second one can be also a SSE =
register or=20
128-bit memory location. Memory operands for <SPAN =
class=3Dsmallcode>movdqa</SPAN>=20
instruction must be aligned on boundary of 16 bytes, operands for <SPAN=20
class=3Dsmallcode>movdqu</SPAN> instruction don't have to be aligned. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movq2dq</SPAN> moves the =
contents of=20
the MMX source register to the low quad word of destination SSE =
register. <SPAN=20
class=3Dsmallcode>movdq2q</SPAN> moves the low quad word from the source =
SSE=20
register to the destination MMX register. </P><PRE class=3Dsmallcode>    =
movq2dq xmm0,mm1   ; move from MMX register to SSE register
    movdq2q mm0,xmm1   ; move from SSE register to MMX register
</PRE>
<P class=3Dsmalltext>All MMX instructions operating on the 64-bit packed =
integers=20
(those with mnemonics starting with <SPAN class=3Dsmallcode>p</SPAN>) =
are extended=20
to operate on 128-bit packed integers located in SSE registers. =
Additional=20
syntax for these instructions needs an SSE register where MMX register =
was=20
needed, and the 128-bit memory location or SSE register where 64-bit =
memory=20
location or MMX register were needed. The exception is <SPAN=20
class=3Dsmallcode>pshufw</SPAN> instruction, which doesn't allow =
extended syntax,=20
but has two new variants: <SPAN class=3Dsmallcode>pshufhw</SPAN> and =
<SPAN=20
class=3Dsmallcode>pshuflw</SPAN>, which allow only the extended syntax, =
and=20
perform the same operation as <SPAN class=3Dsmallcode>pshufw</SPAN> on =
the high or=20
low quad words of operands respectively. Also the new instruction <SPAN=20
class=3Dsmallcode>pshufd</SPAN> is introduced, which performs the same =
operation=20
as <SPAN class=3Dsmallcode>pshufw</SPAN>, but on the double words =
instead of=20
words, it allows only the extended syntax. </P><PRE class=3Dsmallcode>   =
 psubb xmm0,[esi]   ; substract 16 packed bytes
    pextrw eax,xmm0,7  ; extract highest word into eax
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>paddq</SPAN> performs the =
addition of=20
packed quad words, <SPAN class=3Dsmallcode>psubq</SPAN> performs the =
substraction=20
of packed quad words, <SPAN class=3Dsmallcode>pmuludq</SPAN> performs an =
unsigned=20
multiplication of low double words from each corresponding quad words =
and=20
returns the results in packed quad words. These instructions follow the =
same=20
rules for operands as the general MMX operations described in <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.14">2.1.14=
</A>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pslldq</SPAN> and <SPAN=20
class=3Dsmallcode>psrldq</SPAN> perform logical shift left or right of =
the double=20
quad word in the destination operand by the amount of bytes specified in =
the=20
source operand. The destination operand should be a SSE register, source =
operand=20
should be an 8-bit immediate value. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>punpckhqdq</SPAN> =
interleaves the high=20
quad word of the source operand and the high quad word of the =
destination=20
operand and writes them to the destination SSE register. <SPAN=20
class=3Dsmallcode>punpcklqdq</SPAN> interleaves the low quad word of the =
source=20
operand and the low quad word of the destination operand and writes them =
to the=20
destination SSE register. The source operand can be a 128-bit memory =
location or=20
SSE register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movntdq</SPAN> stores =
packed integer=20
data from the SSE register to memory using non-temporal hint. The source =
operand=20
should be a SSE register, the destination operand should be a 128-bit =
memory=20
location. <SPAN class=3Dsmallcode>movntpd</SPAN> stores packed double =
precision=20
values from the SSE register to memory using a non-temporal hint. Rules =
for=20
operand are the same. <SPAN class=3Dsmallcode>movnti</SPAN> stores =
integer from a=20
general register to memory using a non-temporal hint. The source operand =
should=20
be a 32-bit general register, the destination operand should be a 32-bit =
memory=20
location. <SPAN class=3Dsmallcode>maskmovdqu</SPAN> stores selected =
bytes from the=20
first operand into a 128-bit memory location using a non-temporal hint. =
Both=20
operands should be a SSE registers, the second operand selects wich =
bytes from=20
the source operand are written to memory. The memory location is pointed =
by DI=20
(or EDI) register in the segment selected by DS and does not need to be =
aligned.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>clflush</SPAN> writes and =
invalidates=20
the cache line associated with the address of byte specified with the =
operand,=20
which should be a 8-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lfence</SPAN> performs a =
serializing=20
operation on all instruction loading from memory that were issued prior =
to it.=20
<SPAN class=3Dsmallcode>mfence</SPAN> performs a serializing operation =
on all=20
instruction accesing memory that were issued prior to it, and so it =
combines the=20
functions of <SPAN class=3Dsmallcode>sfence</SPAN> (described in =
previous section)=20
and <SPAN class=3Dsmallcode>lfence</SPAN> instructions. These =
instructions have no=20
operands. </P>
<P><B><A class=3Dsmalltext name=3D2.1.17>2.1.17 SSE3 instructions</A> =
</B></P>
<P class=3Dsmalltext>Prescott technology introduced some new =
instructions to=20
improve the performance of SSE and SSE2 - this extension is called SSE3. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>fisttp</SPAN> behaves like =
the <SPAN=20
class=3Dsmallcode>fistp</SPAN> instruction and accepts the same =
operands, the only=20
difference is that it always used truncation, irrespective of the =
rounding mode.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movshdup</SPAN> loads into =
destination=20
operand the 128-bit value obtained from the source value of the same =
size by=20
filling the each quad word with the two duplicates of the value in its =
high=20
double word. <SPAN class=3Dsmallcode>movsldup</SPAN> performs the same =
action,=20
except it duplicates the values of low double words. The destination =
operand=20
should be SSE register, the source operand can be SSE register or =
128-bit memory=20
location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movddup</SPAN> loads the =
64-bit source=20
value and duplicates it into high and low quad word of the destination =
operand.=20
The destination operand should be SSE register, the source operand can =
be SSE=20
register or 64-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>lddqu</SPAN> is =
functionally equivalent=20
to <SPAN class=3Dsmallcode>movdqu</SPAN> with memory as source operand, =
but it may=20
improve performance when the source operand crosses a cacheline =
boundary. The=20
destination operand has to be SSE register, the source operand must be =
128-bit=20
memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>addsubps</SPAN> performs =
single=20
precision addition of second and fourth pairs and single precision =
substracion=20
of the first and third pairs of floating point values in the operands. =
<SPAN=20
class=3Dsmallcode>addsubpd</SPAN> performs double precision addition of =
the second=20
pair and double precision substraction of the first pair of floating =
point=20
values in the operand. <SPAN class=3Dsmallcode>haddps</SPAN> performs =
the addition=20
of two single precision values within the each quad word of source and=20
destination operands, and stores the results of such horizontal addition =
of=20
values from destination operand into low quad word of destination =
operand, and=20
the results from the source operand into high quad word of destination =
operand.=20
<SPAN class=3Dsmallcode>haddpd</SPAN> performs the addition of two =
double=20
precision values within each operand, and stores the result from =
destination=20
operand into low quad word of destination operand, and the result from =
source=20
operand into high quad word of destination operand. All these =
instructions need=20
the destination operand to be SSE register, source operand can be SSE =
register=20
or 128-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>monitor</SPAN> sets up an =
address range=20
for monitoring of write-back stores. It need its three operands to be =
EAX, ECX=20
and EDX register in that order. <SPAN class=3Dsmallcode>mwait</SPAN> =
waits for a=20
write-back store to the address range set up by the <SPAN=20
class=3Dsmallcode>monitor</SPAN> instruction. It uses two operands with =
additional=20
parameters, first being the EAX and second the ECX register. </P>
<P class=3Dsmalltext>The functionality of SSE3 is further extended by =
the set of=20
Supplemental SSE3 instructions (SSSE3). They generally follow the same =
rules for=20
operands as all the MMX operations extended by SSE. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>phaddw</SPAN> and <SPAN=20
class=3Dsmallcode>phaddd</SPAN> perform the horizontal additional of the =
pairs of=20
adjacent values from both the source and destination operand, and stores =
the=20
sums into the destination (sums from the source operand go into lower =
part of=20
destination register). They operate on 16-bit or 32-bit chunks, =
respectively.=20
<SPAN class=3Dsmallcode>phaddsw</SPAN> performs the same operation on =
signed=20
16-bit packed values, but the result of each addition is saturated. =
<SPAN=20
class=3Dsmallcode>phsubw</SPAN> and <SPAN =
class=3Dsmallcode>phsubd</SPAN>=20
analogously perform the horizontal substraction of 16-bit or 32-bit =
packed=20
value, and <SPAN class=3Dsmallcode>phsubsw</SPAN> performs the =
horizontal=20
substraction of signed 16-bit packed values with saturation. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pabsb</SPAN>, <SPAN=20
class=3Dsmallcode>pabsw</SPAN> and <SPAN class=3Dsmallcode>pabsd</SPAN> =
calculate=20
the absolute value of each signed packed signed value in source operand =
and=20
stores them into the destination register. They operator on 8-bit, =
16-bit and=20
32-bit elements respectively. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pmaddubsw</SPAN> multiplies =
signed=20
8-bit values from the source operand with the corresponding unsigned =
8-bit=20
values from the destination operand to produce intermediate 16-bit =
values, and=20
every adjacent pair of those intermediate values is then added =
horizontally and=20
those 16-bit sums are stored into the destination operand. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pmulhrsw</SPAN> multiplies=20
corresponding 16-bit integers from the source and destination operand to =
produce=20
intermediate 32-bit values, and the 16 bits next to the highest bit of =
each of=20
those values are then rounded and packed into the destination operand. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pshufb</SPAN> shuffles the =
bytes in the=20
destination operand according to the mask provided by source operand - =
each of=20
the bytes in source operand is an index of the target position for the=20
corresponding byte in the destination. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>psignb</SPAN>, <SPAN=20
class=3Dsmallcode>psignw</SPAN> and <SPAN =
class=3Dsmallcode>psignd</SPAN> perform=20
the operation on 8-bit, 16-bit or 32-bit integers in destination =
operand,=20
depending on the signs of the values in the source. If the value in =
source is=20
negative, the corresponding value in the destination register is =
negated, if the=20
value in source is positive, no operation is performed on the =
corresponding=20
value is performed, and if the value in source is zero, the value in =
destination=20
is zeroed, too. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>palignr</SPAN> appends the =
source=20
operand to the destination operand to form the intermediate value of =
twice the=20
size, and then extracts into the destination register the 64 or 128 bits =
that=20
are right-aligned to the byte offset specified by the third operand, =
which=20
should be an 8-bit immediate value. This is the only SSSE3 instruction =
that=20
takes three arguments. </P>
<P><B><A class=3Dsmalltext name=3D2.1.18>2.1.18 AMD 3DNow! =
instructions</A> </B></P>
<P class=3Dsmalltext>The 3DNow! extension adds a new MMX instructions to =
those=20
described in <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.1.14">2.1.14=
</A>, and=20
introduces operation on the 64-bit packed floating point values, each =
consisting=20
of two single precision floating point values. </P>
<P class=3Dsmalltext>These instructions follow the same rules as the =
general MMX=20
operations, the destination operand should be a MMX register, the source =
operand=20
can be a MMX register or 64-bit memory location. <SPAN=20
class=3Dsmallcode>pavgusb</SPAN> computes the rounded averages of packed =
unsigned=20
bytes. <SPAN class=3Dsmallcode>pmulhrw</SPAN> performs a signed =
multiplication of=20
the packed words, round the high word of each double word results and =
stores=20
them in the destination operand. <SPAN class=3Dsmallcode>pi2fd</SPAN> =
converts=20
packed double word integers into packed floating point values. <SPAN=20
class=3Dsmallcode>pf2id</SPAN> converts packed floating point values =
into packed=20
double word integers using truncation. <SPAN =
class=3Dsmallcode>pi2fw</SPAN>=20
converts packed word integers into packed floating point values, only =
low words=20
of each double word in source operand are used. <SPAN=20
class=3Dsmallcode>pf2iw</SPAN> converts packed floating point values to =
packed=20
word integers, results are extended to double words using the sign =
extension.=20
<SPAN class=3Dsmallcode>pfadd</SPAN> adds packed floating point values. =
<SPAN=20
class=3Dsmallcode>pfsub</SPAN> and <SPAN class=3Dsmallcode>pfsubr</SPAN> =
substracts=20
packed floating point values, the first one substracts source values =
from=20
destination values, the second one substracts destination values from =
the source=20
values. <SPAN class=3Dsmallcode>pfmul</SPAN> multiplies packed floating =
point=20
values. <SPAN class=3Dsmallcode>pfacc</SPAN> adds the low and high =
floating point=20
values of the destination operand, storing the result in the low double =
word of=20
destination, and adds the low and high floating point values of the =
source=20
operand, storing the result in the high double word of destination. =
<SPAN=20
class=3Dsmallcode>pfnacc</SPAN> substracts the high floating point value =
of the=20
destination operand from the low, storing the result in the low double =
word of=20
destination, and substracts the high floating point value of the source =
operand=20
from the low, storing the result in the high double word of destination. =
<SPAN=20
class=3Dsmallcode>pfpnacc</SPAN> substracts the high floating point =
value of the=20
destination operand from the low, storing the result in the low double =
word of=20
destination, and adds the low and high floating point values of the =
source=20
operand, storing the result in the high double word of destination. =
<SPAN=20
class=3Dsmallcode>pfmax</SPAN> and <SPAN class=3Dsmallcode>pfmin</SPAN> =
compute the=20
maximum and minimum of floating point values. <SPAN=20
class=3Dsmallcode>pswapd</SPAN> reverses the high and low double word of =
the=20
source operand. <SPAN class=3Dsmallcode>pfrcp</SPAN> returns an =
estimates of the=20
reciprocals of floating point values from the source operand, <SPAN=20
class=3Dsmallcode>pfrsqrt</SPAN> returns an estimates of the reciprocal =
square=20
roots of floating point values from the source operand, <SPAN=20
class=3Dsmallcode>pfrcpit1</SPAN> performs the first step in the =
Newton-Raphson=20
iteration to refine the reciprocal approximation produced by <SPAN=20
class=3Dsmallcode>pfrcp</SPAN> instruction, <SPAN =
class=3Dsmallcode>pfrsqit1</SPAN>=20
performs the first step in the Newton-Raphson iteration to refine the =
reciprocal=20
square root approximation produced by <SPAN =
class=3Dsmallcode>pfrsqrt</SPAN>=20
instruction, <SPAN class=3Dsmallcode>pfrcpit2</SPAN> performs the second =
final=20
step in the Newton-Raphson iteration to refine the reciprocal =
approximation or=20
the reciprocal square root approximation. <SPAN =
class=3Dsmallcode>pfcmpeq</SPAN>,=20
<SPAN class=3Dsmallcode>pfcmpge</SPAN> and <SPAN =
class=3Dsmallcode>pfcmpgt</SPAN>=20
compare the packed floating point values and sets all bits or zeroes all =
bits of=20
the correspoding data element in the destination operand according to =
the result=20
of comparision, first checks whether values are equal, second checks =
whether=20
destination value is greater or equal to source value, third checks =
whether=20
destination value is greater than source value. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>prefetch</SPAN> and <SPAN=20
class=3Dsmallcode>prefetchw</SPAN> load the line of data from memory =
that contains=20
byte specified with the operand into the data cache, <SPAN=20
class=3Dsmallcode>prefetchw</SPAN> instruction should be used when the =
data in the=20
cache line is expected to be modified, otherwise the <SPAN=20
class=3Dsmallcode>prefetch</SPAN> instruction should be used. The =
operand should=20
be an 8-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>femms</SPAN> performs a =
fast clear of=20
MMX state. This instruction has no operands. </P>
<P><B><A class=3Dsmalltext name=3D2.1.19>2.1.19 The x86-64 long mode=20
instructions</A> </B></P>
<P class=3Dsmalltext>The AMD64 and EM64T architectures (we will use the =
common=20
name x86-64 for them both) extend the x86 instruction set for the 64-bit =

processing. While legacy and compatibility modes use the same set of =
registers=20
and instructions, the new long mode extends the x86 operations to 64 =
bits and=20
introduces several new registers. You can turn on generating the code =
for this=20
mode with the <SPAN class=3Dsmallcode>use64</SPAN> directive. </P>
<P class=3Dsmalltext>Each of the general purpose registers is extended =
to 64 bits=20
and the eight whole new general purpose registers and also eight new SSE =

registers are added. See table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.4">2.4</A> =
for the=20
summary of new registers (only the ones that was not listed in table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_1.2">1.2</A>)=
. The=20
general purpose registers of smallers sizes are the low order portions =
of the=20
larger ones. You can still access the <SPAN class=3Dsmallcode>ah</SPAN>, =
<SPAN=20
class=3Dsmallcode>bh</SPAN>, <SPAN class=3Dsmallcode>ch</SPAN> and <SPAN =

class=3Dsmallcode>dh</SPAN> registers in long mode, but you cannot use =
them in the=20
same instruction with any of the new registers. </P>
<P class=3Dsmalltext><B><A name=3D_2.4>Table 2.4 New registers in long =
mode</A></B>=20
</P>
<TABLE style=3D"WIDTH: 270px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH style=3D"WIDTH: 70px">Type</TH>
    <TD colSpan=3D4>General</TD>
    <TD>SSE</TD>
    <TD>AVX</TD></TR>
  <TR>
    <TH style=3D"WIDTH: 70px">Bits</TH>
    <TD>8</TD>
    <TD>16</TD>
    <TD>32</TD>
    <TD>64</TD>
    <TD>128</TD>
    <TD>256</TD></TR>
  <TR>
    <TD></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>spl</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>bpl</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>sil</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>dil</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r8b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r9b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r10b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r11b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r12b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r13b</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r14b</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>r15b</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r8w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r9w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r10w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r11w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r12w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r13w</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r14w</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>r15w</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r8d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r9d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r10d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r11d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r12d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r13d</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r14d</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>r15d</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>rax</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rcx</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rdx</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rbx</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rsp</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rbp</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rsi</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>rdi</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r8</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r9</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r10</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r11</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r12</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r13</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>r14</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>r15</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm8</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm9</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm10</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm11</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm12</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm13</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>xmm14</SPAN></TD></TR>
        <TR>
          <TD><SPAN =
class=3Dsmallcode>xmm15</SPAN></TD></TR></TBODY></TABLE></TD>
    <TD>
      <TABLE class=3Dintable>
        <TBODY>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>&nbsp;</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm8</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm9</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm10</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm11</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm12</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm13</SPAN></TD></TR>
        <TR>
          <TD><SPAN class=3Dsmallcode>ymm14</SPAN></TD></TR>
        <TR>
          <TD><SPAN=20
  =
class=3Dsmallcode>ymm15</SPAN></TD></TR></TBODY></TABLE></TD></TR></TBODY=
></TABLE>
<P class=3Dsmalltext>In general any instruction from x86 architecture, =
which=20
allowed 16-bit or 32-bit operand sizes, in long mode allows also the =
64-bit=20
operands. The 64-bit registers should be used for addressing in long =
mode, the=20
32-bit addressing is also allowed, but it's not possible to use the =
addresses=20
based on 16-bit registers. Below are the samples of new operations =
possible in=20
long mode on the example of <SPAN class=3Dsmallcode>mov</SPAN> =
instruction: </P><PRE class=3Dsmallcode>    mov rax,r8   ; transfer =
64-bit general register
    mov al,[rbx] ; transfer memory addressed by 64-bit register
</PRE>
<P class=3Dsmalltext>The long mode uses also the instruction pointer =
based=20
addresses, you can specify it manually with the special RIP register =
symbol, but=20
such addressing is also automatically generated by flat assembler, since =
there=20
is no 64-bit absolute addressing in long mode. You can still force the =
assembler=20
to use the 32-bit absolute addressing by putting the <SPAN=20
class=3Dsmallcode>dword</SPAN> size override for address inside the =
square=20
brackets. There is also one exception, where the 64-bit absolute =
addressing is=20
possible, it's the <SPAN class=3Dsmallcode>mov</SPAN> instruction with =
one of the=20
operand being accumulator register, and second being the memory operand. =
To=20
force the assembler to use the 64-bit absolute addressing there, use the =
<SPAN=20
class=3Dsmallcode>qword</SPAN> size operator for address inside the =
square=20
brackets. When no size operator is applied to address, assembler =
generates the=20
optimal form automatically. </P><PRE class=3Dsmallcode>    mov [qword =
0],rax  ; absolute 64-bit addressing
    mov [dword 0],r15d ; absolute 32-bit addressing
    mov [0],rsi        ; automatic RIP-relative addressing
    mov [rip+3],sil    ; manual RIP-relative addressing
</PRE>
<P class=3Dsmalltext>Also as the immediate operands for 64-bit =
operations only the=20
signed 32-bit values are possible, with the only exception being the =
<SPAN=20
class=3Dsmallcode>mov</SPAN> instruction with destination operand being =
64-bit=20
general purpose register. Trying to force the 64-bit immediate with any =
other=20
instruction will cause an error. </P>
<P class=3Dsmalltext>If any operation is performed on the 32-bit general =
registers=20
in long mode, the upper 32 bits of the 64-bit registers containing them =
are=20
filled with zeros. This is unlike the operations on 16-bit or 8-bit =
portions of=20
those registers, which preserve the upper bits. </P>
<P class=3Dsmalltext>Three new type conversion instructions are =
available. The=20
<SPAN class=3Dsmallcode>cdqe</SPAN> sign extends the double word in EAX =
into quad=20
word and stores the result in RAX register. <SPAN =
class=3Dsmallcode>cqo</SPAN>=20
sign extends the quad word in RAX into double quad word and stores the =
extra=20
bits in the RDX register. These instructions have no operands. <SPAN=20
class=3Dsmallcode>movsxd</SPAN> sign extends the double word source =
operand, being=20
either the 32-bit register or memory, into 64-bit destination operand, =
which has=20
to be register. No analogous instruction is needed for the zero =
extension, since=20
it is done automatically by any operations on 32-bit registers, as noted =
in=20
previous paragraph. And the <SPAN class=3Dsmallcode>movzx</SPAN> and =
<SPAN=20
class=3Dsmallcode>movsx</SPAN> instructions, conforming to the general =
rule, can=20
be used with 64-bit destination operand, allowing extension of byte or =
word=20
values into quad words. </P>
<P class=3Dsmalltext>All the binary arithmetic and logical instruction =
are=20
promoted to allow 64-bit operands in long mode. The use of decimal =
arithmetic=20
instructions in long mode prohibited. </P>
<P class=3Dsmalltext>The stack operations, like <SPAN =
class=3Dsmallcode>push</SPAN>=20
and <SPAN class=3Dsmallcode>pop</SPAN> in long mode default to 64-bit =
operands and=20
it's not possible to use 32-bit operands with them. The <SPAN=20
class=3Dsmallcode>pusha</SPAN> and <SPAN class=3Dsmallcode>popa</SPAN> =
are=20
disallowed in long mode. </P>
<P class=3Dsmalltext>The indirect near jumps and calls in long mode =
default to=20
64-bit operands and it's not possible to use the 32-bit operands with =
them. On=20
the other hand, the indirect far jumps and calls allow any operands that =
were=20
allowed by the x86 architecture and also 80-bit memory operand is =
allowed=20
(though only EM64T seems to implement such variant), with the first =
eight bytes=20
defining the offset and two last bytes specifying the selector. The =
direct far=20
jumps and calls are not allowed in long mode. </P>
<P class=3Dsmalltext>The I/O instructions, <SPAN =
class=3Dsmallcode>in</SPAN>, <SPAN=20
class=3Dsmallcode>out</SPAN>, <SPAN class=3Dsmallcode>ins</SPAN> and =
<SPAN=20
class=3Dsmallcode>outs</SPAN> are the exceptional instructions that are =
not=20
extended to accept quad word operands in long mode. But all other string =

operations are, and there are new short forms <SPAN=20
class=3Dsmallcode>movsq</SPAN>, <SPAN class=3Dsmallcode>cmpsq</SPAN>, =
<SPAN=20
class=3Dsmallcode>scasq</SPAN>, <SPAN class=3Dsmallcode>lodsq</SPAN> and =
<SPAN=20
class=3Dsmallcode>stosq</SPAN> introduced for the variants of string =
operations=20
for 64-bit string elements. The RSI and RDI registers are used by =
default to=20
address the string elements. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>lfs</SPAN>, <SPAN=20
class=3Dsmallcode>lgs</SPAN> and <SPAN class=3Dsmallcode>lss</SPAN> =
instructions are=20
extended to accept 80-bit source memory operand with 64-bit destination =
register=20
(though only EM64T seems to implement such variant). The <SPAN=20
class=3Dsmallcode>lds</SPAN> and <SPAN class=3Dsmallcode>les</SPAN> are =
disallowed=20
in long mode. </P>
<P class=3Dsmalltext>The system instructions like <SPAN=20
class=3Dsmallcode>lgdt</SPAN> which required the 48-bit memory operand, =
in long=20
mode require the 80-bit memory operand. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>cmpxchg16b</SPAN> is =
the 64-bit=20
equivalent of <SPAN class=3Dsmallcode>cmpxchg8b</SPAN> instruction, it =
uses the=20
double quad word memory operand and 64-bit registers to perform the =
analoguous=20
operation. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>fxsave64</SPAN> and =
<SPAN=20
class=3Dsmallcode>fxrstor64</SPAN> are new variants of <SPAN=20
class=3Dsmallcode>fxsave</SPAN> and <SPAN =
class=3Dsmallcode>fxrstor</SPAN>=20
instructions, available only in long mode, which use a different format =
of=20
storage area in order to store some pointers in full 64-bit size. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>swapgs</SPAN> is the new =
instruction,=20
which swaps the contents of GS register and the KernelGSbase =
model-specific=20
register (MSR address 0C0000102h). </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>syscall</SPAN> and <SPAN=20
class=3Dsmallcode>sysret</SPAN> is the pair of new instructions that =
provide the=20
functionality similar to <SPAN class=3Dsmallcode>sysenter</SPAN> and =
<SPAN=20
class=3Dsmallcode>sysexit</SPAN> in long mode, where the latter pair is=20
disallowed. The <SPAN class=3Dsmallcode>sysexitq</SPAN> and <SPAN=20
class=3Dsmallcode>sysretq</SPAN> mnemonics provide the 64-bit versions =
of <SPAN=20
class=3Dsmallcode>sysexit</SPAN> and <SPAN =
class=3Dsmallcode>sysret</SPAN>=20
instructions. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>rdmsrq</SPAN> and <SPAN =

class=3Dsmallcode>wrmsrq</SPAN> mnemonics are the 64-bit variants of the =
<SPAN=20
class=3Dsmallcode>rdmsr</SPAN> and <SPAN class=3Dsmallcode>wrmsr</SPAN>=20
instructions. </P>
<P><B><A class=3Dsmalltext name=3D2.1.20>2.1.20 SSE4 instructions</A> =
</B></P>
<P class=3Dsmalltext>There are actually three different sets of =
instructions under=20
the name SSE4. Intel designed two of them, SSE4.1 and SSE4.2, with =
latter=20
extending the former into the full Intel's SSE4 set. On the other hand, =
the=20
implementation by AMD includes only a few instructions from this set, =
but also=20
contains some additional instructions, that are called the SSE4a set. =
</P>
<P class=3Dsmalltext>The SSE4.1 instructions mostly follow the same =
rules for=20
operands, as the basic SSE operations, so they require destination =
operand to be=20
SSE register and source operand to be 128-bit memory location or SSE =
register,=20
and some operations require a third operand, the 8-bit immediate value. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pmulld</SPAN> performs a =
signed=20
multiplication of the packed double words and stores the low double =
words of the=20
results in the destination operand. <SPAN =
class=3Dsmallcode>pmuldq</SPAN> performs=20
a two signed multiplications of the corresponding double words in the =
lower quad=20
words of operands, and stores the results as packed quad words into the=20
destination register. <SPAN class=3Dsmallcode>pminsb</SPAN> and <SPAN=20
class=3Dsmallcode>pmaxsb</SPAN> return the minimum or maximum values of =
packed=20
signed bytes, <SPAN class=3Dsmallcode>pminuw</SPAN> and <SPAN=20
class=3Dsmallcode>pmaxuw</SPAN> return the minimum and maximum values of =
packed=20
unsigned words, <SPAN class=3Dsmallcode>pminud</SPAN>, <SPAN=20
class=3Dsmallcode>pmaxud</SPAN>, <SPAN class=3Dsmallcode>pminsd</SPAN> =
and <SPAN=20
class=3Dsmallcode>pmaxsd</SPAN> return minimum or maximum values of =
packed=20
unsigned or signed words. These instructions complement the instructions =

computing packed minimum or maximum introduced by SSE. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>ptest</SPAN> sets the ZF =
flag to one=20
when the result of bitwise AND of the both operands is zero, and zeroes =
the ZF=20
otherwise. It also sets CF flag to one, when the result of bitwise AND =
of the=20
destination operand with the bitwise NOT of the source operand is zero, =
and=20
zeroes the CF otherwise. <SPAN class=3Dsmallcode>pcmpeqq</SPAN> compares =
packed=20
quad words for equality, and fills the corresponding elements of =
destination=20
operand with either ones or zeros, depending on the result of =
comparison. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>packusdw</SPAN> converts =
packed signed=20
double words from both the source and destination operand into the =
unsigned=20
words using saturation, and stores the eight resulting word values into =
the=20
destination register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>phminposuw</SPAN> finds the =
minimum=20
unsigned word value in source operand and places it into the lowest word =
of=20
destination operand, setting the remaining upper bits of destination to =
zero.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>roundps</SPAN>, <SPAN=20
class=3Dsmallcode>roundss</SPAN>, <SPAN class=3Dsmallcode>roundpd</SPAN> =
and <SPAN=20
class=3Dsmallcode>roundsd</SPAN> perform the rounding of packed or =
individual=20
floating point value of single or double precision, using the rounding =
mode=20
specified by the third operand. </P><PRE class=3Dsmallcode>    roundsd =
xmm0,xmm1,0011b ; round toward zero
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>dpps</SPAN> calculates dot =
product of=20
packed single precision floating point values, that is it multiplies the =

corresponding pairs of values from source and destination operand and =
then sums=20
the products up. The high four bits of the 8-bit immediate third operand =
control=20
which products are calculated and taken to the sum, and the low four =
bits=20
control, into which elements of destination the resulting dot product is =
copied=20
(the other elements are filled with zero). <SPAN =
class=3Dsmallcode>dppd</SPAN>=20
calculates dot product of packed double precision floating point values. =
The=20
bits 4 and 5 of third operand control, which products are calculated and =
added,=20
and bits 0 and 1 of this value control, which elements in destination =
register=20
should get filled with the result. <SPAN =
class=3Dsmallcode>mpsadbw</SPAN>=20
calculates multiple sums of absolute differences of unsigned bytes. The =
third=20
operand controls, with value in bits 0-1, which of the four-byte blocks =
in=20
source operand is taken to calculate the absolute differencies, and with =
value=20
in bit 2, at which of the two first four-byte block in destination =
operand start=20
calculating multiple sums. The sum is calculated from four absolute =
differencies=20
between the corresponding unsigned bytes in the source and destination =
block,=20
and each next sum is calculated in the same way, but taking the four =
bytes from=20
destination at the position one byte after the position of previous =
block. The=20
four bytes from the source stay the same each time. This way eight sums =
of=20
absolute differencies are calculated and stored as packed word values =
into the=20
destination operand. The instructions described in this paragraph follow =
the=20
same rules for operands, as <SPAN class=3Dsmallcode>roundps</SPAN> =
instruction.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>blendps</SPAN>, <SPAN=20
class=3Dsmallcode>blendvps</SPAN>, <SPAN =
class=3Dsmallcode>blendpd</SPAN> and <SPAN=20
class=3Dsmallcode>blendvpd</SPAN> conditionally copy the values from =
source=20
operand into the destination operand, depending on the bits of the mask =
provided=20
by third operand. If a mask bit is set, the corresponding element of =
source is=20
copied into the same place in destination, otherwise this position is=20
destination is left unchanged. The rules for the first two operands are =
the=20
same, as for general SSE instructions. <SPAN =
class=3Dsmallcode>blendps</SPAN> and=20
<SPAN class=3Dsmallcode>blendpd</SPAN> need third operand to be 8-bit =
immediate,=20
and they operate on single or double precision values, respectively. =
<SPAN=20
class=3Dsmallcode>blendvps</SPAN> and <SPAN =
class=3Dsmallcode>blendvpd</SPAN>=20
require third operand to be the XMM0 register. </P><PRE =
class=3Dsmallcode>    blendvps xmm3,xmm7,xmm0 ; blend according to mask
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pblendw</SPAN> =
conditionally copies=20
word elements from the source operand into the destination, depending on =
the=20
bits of mask provided by third operand, which needs to be 8-bit =
immediate value.=20
<SPAN class=3Dsmallcode>pblendvb</SPAN> conditionally copies byte =
elements from=20
the source operands into destination, depending on mask defined by the =
third=20
operand, which has to be XMM0 register. These instructions follow the =
same rules=20
for operands as <SPAN class=3Dsmallcode>blendps</SPAN> and <SPAN=20
class=3Dsmallcode>blendvps</SPAN> instructions, respectively. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>insertps</SPAN> inserts a =
single=20
precision floating point value taken from the position in source operand =

specified by bits 6-7 of third operand into location in destination =
register=20
selected by bits 4-5 of third operand. Additionally, the low four bits =
of third=20
operand control, which elements in destination register will be set to =
zero. The=20
first two operands follow the same rules as for the general SSE =
operation, the=20
third operand should be 8-bit immediate. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>extractps</SPAN> extracts a =
single=20
precision floating point value taken from the location in source operand =

specified by low two bits of third operand, and stores it into the =
destination=20
operand. The destination can be a 32-bit memory value or general purpose =

register, the source operand must be SSE register, and the third operand =
should=20
be 8-bit immediate value. </P><PRE class=3Dsmallcode>    extractps =
edx,xmm3,3 ; extract the highest value
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pinsrb</SPAN>, <SPAN=20
class=3Dsmallcode>pinsrd</SPAN> and <SPAN =
class=3Dsmallcode>pinsrq</SPAN> copy a=20
byte, double word or quad word from the source operand into the location =
of=20
destination operand determined by the third operand. The destination =
operand has=20
to be SSE register, the source operand can be a memory location of =
appropriate=20
size, or the 32-bit general purpose register (but 64-bit general purpose =

register for <SPAN class=3Dsmallcode>pinsrq</SPAN>, which is only =
available in=20
long mode), and the third operand has to be 8-bit immediate value. These =

instructions complement the <SPAN class=3Dsmallcode>pinsrw</SPAN> =
instruction=20
operating on SSE register destination, which was introduced by SSE2. =
</P><PRE class=3Dsmallcode>    pinsrd xmm4,eax,1 ; insert double word =
into second position
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pextrb</SPAN>, <SPAN=20
class=3Dsmallcode>pextrw</SPAN>, <SPAN class=3Dsmallcode>pextrd</SPAN> =
and <SPAN=20
class=3Dsmallcode>pextrq</SPAN> copy a byte, word, double word or quad =
word from=20
the location in source operand specified by third operand, into the =
destination.=20
The source operand should be SSE register, the third operand should be =
8-bit=20
immediate, and the destination operand can be memory location of =
appropriate=20
size, or the 32-bit general purpose register (but 64-bit general purpose =

register for <SPAN class=3Dsmallcode>pextrq</SPAN>, which is only =
available in=20
long mode). The <SPAN class=3Dsmallcode>pextrw</SPAN> instruction with =
SSE=20
register as source was already introduced by SSE2, but SSE4 extends it =
to allow=20
memory operand as destination. </P><PRE class=3Dsmallcode>    pextrw =
[ebx],xmm3,7 ; extract highest word into memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pmovsxbw</SPAN> and <SPAN=20
class=3Dsmallcode>pmovzxbw</SPAN> perform sign extension or zero =
extension of=20
eight byte values from the source operand into packed word values in =
destination=20
operand, which has to be SSE register. The source can be 64-bit memory =
or SSE=20
register - when it is register, only its low portion is used. <SPAN=20
class=3Dsmallcode>pmovsxbd</SPAN> and <SPAN =
class=3Dsmallcode>pmovzxbd</SPAN>=20
perform sign extension or zero extension of the four byte values from =
the source=20
operand into packed double word values in destination operand, the =
source can be=20
32-bit memory or SSE register. <SPAN class=3Dsmallcode>pmovsxbq</SPAN> =
and <SPAN=20
class=3Dsmallcode>pmovzxbq</SPAN> perform sign extension or zero =
extension of the=20
two byte values from the source operand into packed quad word values in=20
destination operand, the source can be 16-bit memory or SSE register. =
<SPAN=20
class=3Dsmallcode>pmovsxwd</SPAN> and <SPAN =
class=3Dsmallcode>pmovzxwd</SPAN>=20
perform sign extension or zero extension of the four word values from =
the source=20
operand into packed double words in destination operand, the source can =
be=20
64-bit memory or SSE register. <SPAN class=3Dsmallcode>pmovsxwq</SPAN> =
and <SPAN=20
class=3Dsmallcode>pmovzxwq</SPAN> perform sign extension or zero =
extension of the=20
two word values from the source operand into packed quad words in =
destination=20
operand, the source can be 32-bit memory or SSE register. <SPAN=20
class=3Dsmallcode>pmovsxdq</SPAN> and <SPAN =
class=3Dsmallcode>pmovzxdq</SPAN>=20
perform sign extension or zero extension of the two double word values =
from the=20
source operand into packed quad words in destination operand, the source =
can be=20
64-bit memory or SSE register. </P><PRE class=3Dsmallcode>    pmovzxbq =
xmm0,word [si]  ; zero-extend bytes to quad words
    pmovsxwq xmm0,xmm1       ; sign-extend words to quad words
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movntdqa</SPAN> loads =
double quad word=20
from the source operand to the destination using a non-temporal hint. =
The=20
destination operand should be SSE register, and the source operand =
should be=20
128-bit memory location. </P>
<P class=3Dsmalltext>The SSE4.2, described below, adds not only some new =

operations on SSE registers, but also introduces some completely new=20
instructions operating on general purpose registers only. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pcmpistri</SPAN> compares =
two=20
zero-ended (implicit length) strings provided in its source and =
destination=20
operand and generates an index stored to ECX; <SPAN=20
class=3Dsmallcode>pcmpistrm</SPAN> performs the same comparison and =
generates a=20
mask stored to XMM0. <SPAN class=3Dsmallcode>pcmpestri</SPAN> compares =
two strings=20
of explicit lengths, with length provided in EAX for the destination =
operand and=20
in EDX for the source operand, and generates an index stored to ECX; =
<SPAN=20
class=3Dsmallcode>pcmpestrm</SPAN> performs the same comparision and =
generates a=20
mask stored to XMM0. The source and destination operand follow the same =
rules as=20
for general SSE instructions, the third operand should be 8-bit =
immediate value=20
determining the details of performed operation - refer to Intel =
documentation=20
for information on those details. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pcmpgtq</SPAN> compares =
packed quad=20
words, and fills the corresponding elements of destination operand with =
either=20
ones or zeros, depending on whether the value in destination is greater =
than the=20
one in source, or not. This instruction follows the same rules for =
operands as=20
<SPAN class=3Dsmallcode>pcmpeqq</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>crc32</SPAN> accumulates a =
CRC32 value=20
for the source operand starting with initial value provided by =
destination=20
operand, and stores the result in destination. Unless in long mode, the=20
destination operand should be a 32-bit general purpose register, and the =
source=20
operand can be a byte, word, or double word register or memory location. =
In long=20
mode the destination operand can also be a 64-bit general purpose =
register, and=20
the source operand in such case can be a byte or quad word register or =
memory=20
location. </P><PRE class=3Dsmallcode>    crc32 eax,dl          ; =
accumulate CRC32 on byte value
    crc32 eax,word [ebx]  ; accumulate CRC32 on word value
    crc32 rax,qword [rbx] ; accumulate CRC32 on quad word value
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>popcnt</SPAN> calculates =
the number of=20
bits set in the source operand, which can be 16-bit, 32-bit, or 64-bit =
general=20
purpose register or memory location, and stores this count in the =
destination=20
operand, which has to be register of the same size as source operand. =
The 64-bit=20
variant is available only in long mode. </P><PRE class=3Dsmallcode>    =
popcnt ecx,eax        ; count bits set to 1
</PRE>
<P class=3Dsmalltext>The SSE4a extension, which also includes the <SPAN=20
class=3Dsmallcode>popcnt</SPAN> instruction introduced by SSE4.2, at the =
same time=20
adds the <SPAN class=3Dsmallcode>lzcnt</SPAN> instruction, which follows =
the same=20
syntax, and calculates the count of leading zero bits in source operand =
(if the=20
source operand is all zero bits, the total number of bits in source =
operand is=20
stored in destination). </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>extrq</SPAN> extract the =
sequence of=20
bits from the low quad word of SSE register provided as first operand =
and stores=20
them at the low end of this register, filling the remaining bits in the =
low quad=20
word with zeros. The position of bit string and its length can either be =

provided with two 8-bit immediate values as second and third operand, or =
by SSE=20
register as second operand (and there is no third operand in such case), =
which=20
should contain position value in bits 8-13 and length of bit string in =
bits 0-5.=20
</P><PRE class=3Dsmallcode>    extrq xmm0,8,7        ; extract 8 bits =
from position 7
    extrq xmm0,xmm5       ; extract bits defined by register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>insertq</SPAN> writes the =
sequence of=20
bits from the low quad word of the source operand into specified =
position in low=20
quad word of the destination operand, leaving the other bits in low quad =
word of=20
destination intact. The position where bits should be written and the =
length of=20
bit string can either be provided with two 8-bit immediate values as =
third and=20
fourth operand, or by the bit fields in source operand (and there are =
only two=20
operands in such case), which should contain position value in bits =
72-77 and=20
length of bit string in bits 64-69. </P><PRE class=3Dsmallcode>    =
insertq xmm1,xmm0,4,2 ; insert 4 bits at position 2
    insertq xmm1,xmm0     ; insert bits defined by register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>movntss</SPAN> and <SPAN=20
class=3Dsmallcode>movntsd</SPAN> store single or double precision =
floating point=20
value from the source SSE register into 32-bit or 64-bit destination =
memory=20
location respectively, using non-temporal hint. </P>
<P><B><A class=3Dsmalltext name=3D2.1.21>2.1.21 AVX instructions</A> =
</B></P>
<P class=3Dsmalltext>The Advanced Vector Extensions introduce =
instructions that=20
are new variants of SSE instructions, with new scheme of encoding that =
allows=20
extended syntax having a destination operand separate from all the =
source=20
operands. It also introduces 256-bit AVX registers, which extend up the =
old=20
128-bit SSE registers. Any AVX instruction that puts some result into =
SSE=20
register, puts zero bits into high portion of the AVX register =
containing it.=20
</P>
<P class=3Dsmalltext>The AVX version of SSE instruction has the mnemonic =
obtained=20
by prepending SSE instruction name with <SPAN =
class=3Dsmallcode>v</SPAN>. For any=20
SSE arithmetic instruction which had a destination operand also being =
used as=20
one of the source values, the AVX variant has a new syntax with three =
operands -=20
the destination and two sources. The destination and first source can be =
SSE=20
registers, and second source can be SSE register or memory. If the =
operation is=20
performed on single pair of values, the remaining bits of first source =
SSE=20
register are copied into the the destination register. </P><PRE =
class=3Dsmallcode>    vsubss xmm0,xmm2,xmm3         ; substract two =
32-bit floats
    vmulsd xmm0,xmm7,qword [esi]  ; multiply two 64-bit floats
</PRE>
<P class=3Dsmalltext>In case of packed operations, each instruction can =
also=20
operate on the 256-bit data size when the AVX registers are specified =
instead of=20
SSE registers, and the size of memory operand is also doubled then. =
</P><PRE class=3Dsmallcode>    vaddps ymm1,ymm5,yword [esi]  ; eight =
sums of 32-bit float pairs
</PRE>
<P class=3Dsmalltext>The instructions that operate on packed integer =
types (in=20
particular the ones that earlier had been promoted from MMX to SSE) also =

acquired the new syntax with three operands, however they are only =
allowed to=20
operate on 128-bit packed types and thus cannot use the whole AVX =
registers.=20
</P><PRE class=3Dsmallcode>    vpavgw xmm3,xmm0,xmm2         ; average =
of 16-bit integers
    vpslld xmm1,xmm0,1            ; shift double words left
</PRE>
<P class=3Dsmalltext>If the SSE version of instruction had a syntax with =
three=20
operands, the third one being an immediate value, the AVX version of =
such=20
instruction takes four operands, with immediate remaining the last one. =
</P><PRE class=3Dsmallcode>    vshufpd ymm0,ymm1,ymm2,10010011b ; =
shuffle 64-bit floats
    vpalignr xmm0,xmm4,xmm2,3        ; extract byte aligned value
</PRE>
<P class=3Dsmalltext>The promotion to new syntax according to the rules =
described=20
above has been applied to all the instructions from SSE extensions up to =
SSE4,=20
with the exceptions described below. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vdppd</SPAN> instruction =
has syntax=20
extended to four operans, but it does not have a 256-bit version. </P>
<P class=3Dsmalltext>The are a few instructions, namely <SPAN=20
class=3Dsmallcode>vsqrtpd</SPAN>, <SPAN =
class=3Dsmallcode>vsqrtps</SPAN>, <SPAN=20
class=3Dsmallcode>vrcpps</SPAN> and <SPAN =
class=3Dsmallcode>vrsqrtps</SPAN>, which=20
can operate on 256-bit data size, but retained the syntax with only two=20
operands, because they use data from only one source: </P><PRE =
class=3Dsmallcode>    vsqrtpd ymm1,ymm0         ; put square roots into =
other register
</PRE>
<P class=3Dsmalltext>In a similar way <SPAN =
class=3Dsmallcode>vroundpd</SPAN> and=20
<SPAN class=3Dsmallcode>vroundps</SPAN> retained the syntax with three =
operands,=20
the last one being immediate value. </P><PRE class=3Dsmallcode>    =
vroundps ymm0,ymm1,0011b  ; round toward zero
</PRE>
<P class=3Dsmalltext>Also some of the operations on packed integers kept =
their=20
two-operand or three-operand syntax while being promoted to AVX version. =
In such=20
case these instructions follow exactly the same rules for operands as =
their SSE=20
counterparts (since operations on packed integers do not have 256-bit =
variants=20
in AVX extension). These include <SPAN =
class=3Dsmallcode>vpcmpestri</SPAN>, <SPAN=20
class=3Dsmallcode>vpcmpestrm</SPAN>, <SPAN =
class=3Dsmallcode>vpcmpistri</SPAN>,=20
<SPAN class=3Dsmallcode>vpcmpistrm</SPAN>, <SPAN=20
class=3Dsmallcode>vphminposuw</SPAN>, <SPAN =
class=3Dsmallcode>vpshufd</SPAN>, <SPAN=20
class=3Dsmallcode>vpshufhw</SPAN>, <SPAN =
class=3Dsmallcode>vpshuflw</SPAN>. And=20
there are more instructions that in AVX versions keep exactly the same =
syntax=20
for operands as the one from SSE, without any additional options: <SPAN=20
class=3Dsmallcode>vcomiss</SPAN>, <SPAN =
class=3Dsmallcode>vcomisd</SPAN>, <SPAN=20
class=3Dsmallcode>vcvtss2si</SPAN>, <SPAN =
class=3Dsmallcode>vcvtsd2si</SPAN>, <SPAN=20
class=3Dsmallcode>vcvttss2si</SPAN>, <SPAN =
class=3Dsmallcode>vcvttsd2si</SPAN>,=20
<SPAN class=3Dsmallcode>vextractps</SPAN>, <SPAN =
class=3Dsmallcode>vpextrb</SPAN>,=20
<SPAN class=3Dsmallcode>vpextrw</SPAN>, <SPAN =
class=3Dsmallcode>vpextrd</SPAN>,=20
<SPAN class=3Dsmallcode>vpextrq</SPAN>, <SPAN =
class=3Dsmallcode>vmovd</SPAN>, <SPAN=20
class=3Dsmallcode>vmovq</SPAN>, <SPAN =
class=3Dsmallcode>vmovntdqa</SPAN>, <SPAN=20
class=3Dsmallcode>vmaskmovdqu</SPAN>, <SPAN =
class=3Dsmallcode>vpmovmskb</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovsxbw</SPAN>, <SPAN =
class=3Dsmallcode>vpmovsxbd</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovsxbq</SPAN>, <SPAN =
class=3Dsmallcode>vpmovsxwd</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovsxwq</SPAN>, <SPAN =
class=3Dsmallcode>vpmovsxdq</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovzxbw</SPAN>, <SPAN =
class=3Dsmallcode>vpmovzxbd</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovzxbq</SPAN>, <SPAN =
class=3Dsmallcode>vpmovzxwd</SPAN>,=20
<SPAN class=3Dsmallcode>vpmovzxwq</SPAN> and <SPAN=20
class=3Dsmallcode>vpmovzxdq</SPAN>. </P>
<P class=3Dsmalltext>The move and conversion instructions have mostly =
been=20
promoted to allow 256-bit size operands in addition to the 128-bit =
variant with=20
syntax identical to that from SSE version of the same instruction. Each =
of the=20
<SPAN class=3Dsmallcode>vcvtdq2ps</SPAN>, <SPAN =
class=3Dsmallcode>vcvtps2dq</SPAN>=20
and <SPAN class=3Dsmallcode>vcvttps2dq</SPAN>, <SPAN=20
class=3Dsmallcode>vmovaps</SPAN>, <SPAN =
class=3Dsmallcode>vmovapd</SPAN>, <SPAN=20
class=3Dsmallcode>vmovups</SPAN>, <SPAN =
class=3Dsmallcode>vmovupd</SPAN>, <SPAN=20
class=3Dsmallcode>vmovdqa</SPAN>, <SPAN =
class=3Dsmallcode>vmovdqu</SPAN>, <SPAN=20
class=3Dsmallcode>vlddqu</SPAN>, <SPAN =
class=3Dsmallcode>vmovntps</SPAN>, <SPAN=20
class=3Dsmallcode>vmovntpd</SPAN>, <SPAN =
class=3Dsmallcode>vmovntdq</SPAN>, <SPAN=20
class=3Dsmallcode>vmovsldup</SPAN>, <SPAN =
class=3Dsmallcode>vmovshdup</SPAN>, <SPAN=20
class=3Dsmallcode>vmovmskps</SPAN> and <SPAN =
class=3Dsmallcode>vmovmskpd</SPAN>=20
inherits the 128-bit syntax from SSE without any changes, and also =
allows a new=20
form with 256-bit operands in place of 128-bit ones. </P><PRE =
class=3Dsmallcode>    vmovups [edi],ymm6        ; store unaligned =
256-bit data
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmovddup</SPAN> has the =
identical=20
128-bit syntax as its SSE version, and it also has a 256-bit version, =
which=20
stores the duplicates of the lowest quad word from the source operand in =
the=20
lower half of destination operand, and in the upper half of destination =
the=20
duplicates of the low quad word from the upper half of source. Both =
source and=20
destination operands need then to be 256-bit values. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmovlhps</SPAN> and <SPAN=20
class=3Dsmallcode>vmovhlps</SPAN> have only 128-bit versions, and each =
takes three=20
operands, which all must be SSE registers. <SPAN =
class=3Dsmallcode>vmovlhps</SPAN>=20
copies two single precision values from the low quad word of second =
source=20
register to the high quad word of destination register, and copies the =
low quad=20
word of first source register into the low quad word of destination =
register.=20
<SPAN class=3Dsmallcode>vmovhlps</SPAN> copies two single precision =
values from=20
the high quad word of second source register to the low quad word of =
destination=20
register, and copies the high quad word of first source register into =
the high=20
quad word of destination register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmovlps</SPAN>, <SPAN=20
class=3Dsmallcode>vmovhps</SPAN>, <SPAN class=3Dsmallcode>vmovlpd</SPAN> =
and <SPAN=20
class=3Dsmallcode>vmovhpd</SPAN> have only 128-bit versions and their =
syntax=20
varies depending on whether memory operand is a destination or source. =
When=20
memory is destination, the syntax is identical to the one of equivalent =
SSE=20
instruction, and when memory is source, the instruction requires three =
operands,=20
first two being SSE registers and the third one 64-bit memory. The value =
put=20
into destination is then the value copied from first source with either =
low or=20
high quad word replaced with value from second source (the memory =
operand). </P><PRE class=3Dsmallcode>    vmovhps [esi],xmm7       ; =
store upper half to memory
    vmovlps xmm0,xmm7,[ebx]  ; low from memory, rest from register
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmovss</SPAN> and <SPAN=20
class=3Dsmallcode>vmovsd</SPAN> have syntax identical to their SSE =
equivalents as=20
long as one of the operands is memory, while the versions that operate =
purely on=20
registers require three operands (each being SSE register). The value =
stored in=20
destination is then the value copied from first source with lowest data =
element=20
replaced with the lowest value from second source. </P><PRE =
class=3Dsmallcode>    vmovss xmm3,[edi]        ; low from memory, rest =
zeroed
    vmovss xmm0,xmm1,xmm2    ; one value from xmm2, three from xmm1
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vcvtss2sd</SPAN>, <SPAN=20
class=3Dsmallcode>vcvtsd2ss</SPAN>, <SPAN =
class=3Dsmallcode>vcvtsi2ss</SPAN> and=20
<SPAN class=3Dsmallcode>vcvtsi2d</SPAN> use the three-operand syntax, =
where=20
destination and first source are always SSE registers, and the second =
source=20
follows the same rules and the source in syntax of equivalent SSE =
instruction.=20
The value stored in destination is then the value copied from first =
source with=20
lowest data element replaced with the result of conversion. </P><PRE =
class=3Dsmallcode>    vcvtsi2sd xmm4,xmm4,ecx  ; 32-bit integer to =
64-bit float
    vcvtsi2ss xmm0,xmm0,rax  ; 64-bit integer to 32-bit float
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vcvtdq2pd</SPAN> and <SPAN=20
class=3Dsmallcode>vcvtps2pd</SPAN> allow the same syntax as their SSE =
equivalents,=20
plus the new variants with AVX register as destination and SSE register =
or=20
128-bit memory as source. Analogously <SPAN =
class=3Dsmallcode>vcvtpd2dq</SPAN>,=20
<SPAN class=3Dsmallcode>vcvttpd2dq</SPAN> and <SPAN=20
class=3Dsmallcode>vcvtpd2ps</SPAN>, in addition to variant with syntax =
identical=20
to SSE version, allow a variant with SSE register as destination and AVX =

register or 256-bit memory as source. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vinsertps</SPAN>, <SPAN=20
class=3Dsmallcode>vpinsrb</SPAN>, <SPAN =
class=3Dsmallcode>vpinsrw</SPAN>, <SPAN=20
class=3Dsmallcode>vpinsrd</SPAN>, <SPAN class=3Dsmallcode>vpinsrq</SPAN> =
and <SPAN=20
class=3Dsmallcode>vpblendw</SPAN> use a syntax with four operands, where =

destination and first source have to be SSE registers, and the third and =
fourth=20
operand follow the same rules as second and third operand in the syntax =
of=20
equivalent SSE instruction. Value stored in destination is the the value =
copied=20
from first source with some data elements replaced with values extracted =
from=20
the second source, analogously to the operation of corresponding SSE=20
instruction. </P><PRE class=3Dsmallcode>    vpinsrd xmm0,xmm0,eax,3  ; =
insert double word
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vblendvps</SPAN>, <SPAN=20
class=3Dsmallcode>vblendvpd</SPAN> and <SPAN =
class=3Dsmallcode>vpblendvb</SPAN> use=20
a new syntax with four register operands: destination, two sources and a =
mask,=20
where second source can also be a memory operand. <SPAN=20
class=3Dsmallcode>vblendvps</SPAN> and <SPAN =
class=3Dsmallcode>vblendvpd</SPAN> have=20
256-bit variant, where operands are AVX registers or 256-bit memory, as =
well as=20
128-bit variant, which has operands being SSE registers or 128-bit =
memory. <SPAN=20
class=3Dsmallcode>vpblendvb</SPAN> has only a 128-bit variant. Value =
stored in=20
destination is the value copied from the first source with some data =
elements=20
replaced, according to mask, by values from the second source. </P><PRE =
class=3Dsmallcode>    vblendvps ymm3,ymm1,ymm2,ymm7  ; blend according =
to mask
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vptest</SPAN> allows the =
same syntax as=20
its SSE version and also has a 256-bit version, with both operands =
doubled in=20
size. There are also two new instructions, <SPAN =
class=3Dsmallcode>vtestps</SPAN>=20
and <SPAN class=3Dsmallcode>vtestpd</SPAN>, which perform analogous =
tests, but=20
only of the sign bits of corresponding single precision or double =
precision=20
values, and set the ZF and CF accordingly. They follow the same syntax =
rules as=20
<SPAN class=3Dsmallcode>vptest</SPAN>. </P><PRE class=3Dsmallcode>    =
vptest ymm0,yword [ebx]  ; test 256-bit values
    vtestpd xmm0,xmm1        ; test sign bits of 64-bit floats
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vbroadcastss</SPAN>, <SPAN=20
class=3Dsmallcode>vbroadcastsd</SPAN> and <SPAN=20
class=3Dsmallcode>vbroadcastf128</SPAN> are new instructions, which =
broadcast the=20
data element defined by source operand into all elements of corresponing =
size in=20
the destination register. <SPAN class=3Dsmallcode>vbroadcastss</SPAN> =
needs source=20
to be 32-bit memory and destination to be either SSE or AVX register. =
<SPAN=20
class=3Dsmallcode>vbroadcastsd</SPAN> requires 64-bit memory as source, =
and AVX=20
register as destination. <SPAN class=3Dsmallcode>vbroadcastf128</SPAN> =
requires=20
128-bit memory as source, and AVX register as destination. </P><PRE =
class=3Dsmallcode>    vbroadcastss ymm0,dword [eax]  ; get eight copies =
of value
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vinsertf128</SPAN> is the =
new=20
instruction, which takes four operands. The destination and first source =
have to=20
be AVX registers, second source can be SSE register or 128-bit memory =
location,=20
and fourth operand should be an immediate value. It stores in =
destination the=20
value obtained by taking contents of first source and replacing one of =
its=20
128-bit units with value of the second source. The lowest bit of fourth =
operand=20
specifies at which position that replacement is done (either 0 or 1). =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vextractf128</SPAN> is the =
new=20
instruction with three operands. The destination needs to be SSE =
register or=20
128-bit memory location, the source must be AVX register, and the third =
operand=20
should be an immediate value. It extracts into destination one of the =
128-bit=20
units from source. The lowest bit of third operand specifies, which unit =
is=20
extracted. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmaskmovps</SPAN> and <SPAN =

class=3Dsmallcode>vmaskmovpd</SPAN> are the new instructions with three =
operands=20
that selectively store in destination the elements from second source =
depending=20
on the sign bits of corresponding elements from first source. These =
instructions=20
can operate on either 128-bit data (SSE registers) or 256-bit data (AVX=20
registers). Either destination or second source has to be a memory =
location of=20
appropriate size, the two other operands should be registers. </P><PRE =
class=3Dsmallcode>    vmaskmovps [edi],xmm0,xmm5  ; conditionally store
    vmaskmovpd ymm5,ymm0,[esi]  ; conditionally load
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpermilpd</SPAN> and <SPAN=20
class=3Dsmallcode>vpermilps</SPAN> are the new instructions with three =
operands=20
that permute the values from first source according to the control =
fields from=20
second source and put the result into destination operand. It allows to =
use=20
either three SSE registers or three AVX registers as its operands, the =
second=20
source can be a memory of size equal to the registers used. In =
alternative form=20
the second source can be immediate value and then the first source can =
be a=20
memory location of the size equal to destination register. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vperm2f128</SPAN> is the =
new=20
instruction with four operands, which selects 128-bit blocks of floating =
point=20
data from first and second source according to the bit fields from =
fourth=20
operand, and stores them in destination. Destination and first source =
need to be=20
AVX registers, second source can be AVX register or 256-bit memory area, =
and=20
fourth operand should be an immediate value. </P><PRE class=3Dsmallcode> =
   vperm2f128 ymm0,ymm6,ymm7,12h  ; permute 128-bit blocks
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vzeroall</SPAN> instruction =
sets all=20
the AVX registers to zero. <SPAN class=3Dsmallcode>vzeroupper</SPAN> =
sets the=20
upper 128-bit portions of all AVX registers to zero, leaving the SSE =
registers=20
intact. These new instructions take no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vldmxcsr</SPAN> and <SPAN=20
class=3Dsmallcode>vstmxcsr</SPAN> are the AVX versions of <SPAN=20
class=3Dsmallcode>ldmxcsr</SPAN> and <SPAN =
class=3Dsmallcode>stmxcsr</SPAN>=20
instructions. The rules for their operands remain unchanged. </P>
<P><B><A class=3Dsmalltext name=3D2.1.22>2.1.22 AVX2 instructions</A> =
</B></P>
<P class=3Dsmalltext>The AVX2 extension allows all the AVX instructions =
operating=20
on packed integers to use 256-bit data types, and introduces some new=20
instructions as well. </P>
<P class=3Dsmalltext>The AVX instructions that operate on packed =
integers and had=20
only a 128-bit variants, have been supplemented with 256-bit variants, =
and thus=20
their syntax rules became analogous to AVX instructions operating on =
packed=20
floating point types. </P><PRE class=3Dsmallcode>    vpsubb =
ymm0,ymm0,[esi]   ; substract 32 packed bytes
    vpavgw ymm3,ymm0,ymm2    ; average of 16-bit integers
</PRE>
<P class=3Dsmalltext>However there are some instructions that have not =
been=20
equipped with the 256-bit variants. <SPAN =
class=3Dsmallcode>vpcmpestri</SPAN>,=20
<SPAN class=3Dsmallcode>vpcmpestrm</SPAN>, <SPAN=20
class=3Dsmallcode>vpcmpistri</SPAN>, <SPAN =
class=3Dsmallcode>vpcmpistrm</SPAN>,=20
<SPAN class=3Dsmallcode>vpextrb</SPAN>, <SPAN =
class=3Dsmallcode>vpextrw</SPAN>,=20
<SPAN class=3Dsmallcode>vpextrd</SPAN>, <SPAN =
class=3Dsmallcode>vpextrq</SPAN>,=20
<SPAN class=3Dsmallcode>vpinsrb</SPAN>, <SPAN =
class=3Dsmallcode>vpinsrw</SPAN>,=20
<SPAN class=3Dsmallcode>vpinsrd</SPAN>, <SPAN =
class=3Dsmallcode>vpinsrq</SPAN> and=20
<SPAN class=3Dsmallcode>vphminposuw</SPAN> are not affected by AVX2 and =
allow only=20
the 128-bit operands. </P>
<P class=3Dsmalltext>The packed shift instructions, which allowed the =
third=20
operand specifying amount to be SSE register or 128-bit memory location, =
use the=20
same rules for the third operand in their 256-bit variant. </P><PRE =
class=3Dsmallcode>    vpsllw ymm2,ymm2,xmm4        ; shift words left
    vpsrad ymm0,ymm3,xword [ebx] ; shift double words right
</PRE>
<P class=3Dsmalltext>There are also new packed shift instructions with =
standard=20
three-operand AVX syntax, which shift each element from first source by =
the=20
amount specified in corresponding element of second source, and store =
the=20
results in destination. <SPAN class=3Dsmallcode>vpsllvd</SPAN> shifts =
32-bit=20
elements left, <SPAN class=3Dsmallcode>vpsllvq</SPAN> shifts 64-bit =
elements left,=20
<SPAN class=3Dsmallcode>vpsrlvd</SPAN> shifts 32-bit elements right =
logically,=20
<SPAN class=3Dsmallcode>vpsrlvq</SPAN> shifts 64-bit elements right =
logically and=20
<SPAN class=3Dsmallcode>vpsravd</SPAN> shifts 32-bit elements right=20
arithmetically. </P>
<P class=3Dsmalltext>The sign-extend and zero-extend instructions, which =
in AVX=20
versions allowed source operand to be SSE register or a memory of =
specific size,=20
in the new 256-bit variant need memory of that size doubled or SSE =
register as=20
source and AVX register as destination. </P><PRE class=3Dsmallcode>    =
vpmovzxbq ymm0,dword [esi]   ; bytes to quad words
</PRE>
<P class=3Dsmalltext>Also <SPAN class=3Dsmallcode>vmovntdqa</SPAN> has =
been upgraded=20
with 256-bit variant, so it allows to transfer 256-bit value from memory =
to AVX=20
register, it needs memory address to be aligned to 32 bytes. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpmaskmovd</SPAN> and <SPAN =

class=3Dsmallcode>vpmaskmovq</SPAN> are the new instructions with syntax =
identical=20
to <SPAN class=3Dsmallcode>vmaskmovps</SPAN> or <SPAN=20
class=3Dsmallcode>vmaskmovpd</SPAN>, and they performs analogous =
operation on=20
packed 32-bit or 64-bit values. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vinserti128</SPAN>, <SPAN=20
class=3Dsmallcode>vextracti128</SPAN>, <SPAN =
class=3Dsmallcode>vbroadcasti128</SPAN>=20
and <SPAN class=3Dsmallcode>vperm2i128</SPAN> are the new instructions =
with syntax=20
identical to <SPAN class=3Dsmallcode>vinsertf128</SPAN>, <SPAN=20
class=3Dsmallcode>vextractf128</SPAN>, <SPAN =
class=3Dsmallcode>vbroadcastf128</SPAN>=20
and <SPAN class=3Dsmallcode>vperm2f128</SPAN> respectively, and they =
perform=20
analogous operations on 128-bit blocks of integer data. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vbroadcastss</SPAN> and =
<SPAN=20
class=3Dsmallcode>vbroadcastsd</SPAN> instructions have been extended to =
allow SSE=20
register as a source operand (which in AVX could only be a memory). </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpbroadcastb</SPAN>, <SPAN=20
class=3Dsmallcode>vpbroadcastw</SPAN>, <SPAN =
class=3Dsmallcode>vpbroadcastd</SPAN>=20
and <SPAN class=3Dsmallcode>vpbroadcastq</SPAN> are the new instructions =
which=20
broadcast the byte, word, double word or quad word from the source =
operand into=20
all elements of corresponing size in the destination register. The =
destination=20
operand can be either SSE or AVX register, and the source operand can be =
SSE=20
register or memory of size equal to the size of data element. </P><PRE =
class=3Dsmallcode>    vpbroadcastb ymm0,byte [ebx]  ; get 32 identical =
bytes
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpermd</SPAN> and <SPAN=20
class=3Dsmallcode>vpermps</SPAN> are new three-operand instructions, =
which use=20
each 32-bit element from first source as an index of element in second =
source=20
which is copied into destination at position corresponding to element =
containing=20
index. The destination and first source have to be AVX registers, and =
the second=20
source can be AVX register or 256-bit memory. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpermq</SPAN> and <SPAN=20
class=3Dsmallcode>vpermpd</SPAN> are new three-operand instructions, =
which use=20
2-bit indexes from the immediate value specified as third operand to =
determine=20
which element from source store at given position in destination. The=20
destination has to be AVX register, source can be AVX register or =
256-bit=20
memory, and the third operand must be 8-bit immediate value. </P>
<P class=3Dsmalltext>The family of new instructions performing <SPAN=20
class=3Dsmallcode>gather</SPAN> operation have special syntax, as in =
their memory=20
operand they use addressing mode that is unique to them. The base of =
address can=20
be a 32-bit or 64-bit general purpose register (the latter only in long =
mode),=20
and the index (possibly multiplied by scale value, as in standard =
addressing) is=20
specified by SSE or AVX register. It is possible to use only index =
without base=20
and any numerical displacement can be added to the address. Each of =
those=20
instructions takes three operands. First operand is the destination =
register,=20
second operand is memory addressed with a vector index, and third =
operand is=20
register containing a mask. The most significant bit of each element of =
mask=20
determines whether a value will be loaded from memory into corresponding =
element=20
in destination. The address of each element to load is determined by =
using the=20
corresponding element from index register in memory operand to calculate =
final=20
address with given base and displacement. When the index register =
contains less=20
elements than the destination and mask registers, the higher elements of =

destination are zeroed. After the value is successfuly loaded, the =
corresponding=20
element in mask register is set to zero. The destination, index and mask =
should=20
all be distinct registers, it is not allowed to use the same register in =
two=20
different roles. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vgatherdps</SPAN> loads =
single=20
precision floating point values addressed by 32-bit indexes. The =
destination,=20
index and mask should all be registers of the same type, either SSE or =
AVX. The=20
data addressed by memory operand is 32-bit in size. </P><PRE =
class=3Dsmallcode>    vgatherdps xmm0,[eax+xmm1],xmm3    ; gather four =
floats
    vgatherdps ymm0,[ebx+ymm7*4],ymm3  ; gather eight floats
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vgatherqps</SPAN> loads =
single=20
precision floating point values addressed by 64-bit indexes. The =
destination and=20
mask should always be SSE registers, while index register can be either =
SSE or=20
AVX register. The data addressed by memory operand is 32-bit in size. =
</P><PRE class=3Dsmallcode>    vgatherqps xmm0,[xmm2],xmm3        ; =
gather two floats
    vgatherqps xmm0,[ymm2+64],xmm3     ; gather four floats
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vgatherdpd</SPAN> loads =
double=20
precision floating point values addressed by 32-bit indexes. The index =
register=20
should always be SSE register, the destination and mask should be two =
registers=20
of the same type, either SSE or AVX. The data addressed by memory =
operand is=20
64-bit in size. </P><PRE class=3Dsmallcode>    vgatherdpd =
xmm0,[ebp+xmm1],xmm3    ; gather two doubles
    vgatherdpd ymm0,[xmm3*8],ymm5      ; gather four doubles
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vgatherqpd</SPAN> loads =
double=20
precision floating point values addressed by 64-bit indexes. The =
destination,=20
index and mask should all be registers of the same type, either SSE or =
AVX. The=20
data addressed by memory operand is 64-bit in size. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpgatherdd</SPAN> and <SPAN =

class=3Dsmallcode>vpgatherqd</SPAN> load 32-bit values addressed by =
either 32-bit=20
or 64-bit indexes. They follow the same rules as <SPAN=20
class=3Dsmallcode>vgatherdps</SPAN> and <SPAN =
class=3Dsmallcode>vgatherqps</SPAN>=20
respectively. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpgatherdq</SPAN> and <SPAN =

class=3Dsmallcode>vpgatherqq</SPAN> load 64-bit values addressed by =
either 32-bit=20
or 64-bit indexes. They follow the same rules as <SPAN=20
class=3Dsmallcode>vgatherdpd</SPAN> and <SPAN =
class=3Dsmallcode>vgatherqpd</SPAN>=20
respectively. </P>
<P><B><A class=3Dsmalltext name=3D2.1.23>2.1.23 Auxiliary sets of =
computational=20
instructions</A> </B></P>
<P class=3Dsmalltext>There is a number of additional instruction set =
extensions=20
related to AVX. They introduce new vector instructions (and sometimes =
also their=20
SSE equivalents that use classic instruction encoding), and even some =
new=20
instructions operating on general registers that use the AVX-like =
encoding=20
allowing the extended syntax with separate destination and source =
operands. The=20
CPU support for each of these instructions sets needs to be determined=20
separately. </P>
<P class=3Dsmalltext>The AES extension provides a specialized set of =
instructions=20
for the purpose of cryptographic computations defined by Advanced =
Encryption=20
Standard. Each of these instructions has two versions: the AVX one and =
the one=20
with SSE-like syntax that uses classic encoding. Refer to the Intel =
manuals for=20
the details of operation of these instructions. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aesenc</SPAN> and <SPAN=20
class=3Dsmallcode>aesenclast</SPAN> perform a single round of AES =
encryption on=20
data from first source with a round key from second source, and store =
result in=20
destination. The destination and first source are SSE registers, and the =
second=20
source can be SSE register or 128-bit memory. The AVX versions of these=20
instructions, <SPAN class=3Dsmallcode>vaesenc</SPAN> and <SPAN=20
class=3Dsmallcode>vaesenclast</SPAN>, use the syntax with three =
operands, while=20
the SSE-like version has only two operands, with first operand being =
both the=20
destination and first source. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aesdec</SPAN> and <SPAN=20
class=3Dsmallcode>aesdeclast</SPAN> perform a single round of AES =
decryption on=20
data from first source with a round key from second source. The syntax =
rules for=20
them and their AVX versions are the same as for <SPAN=20
class=3Dsmallcode>aesenc</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aesimc</SPAN> performs the=20
InvMixColumns transformation of source operand and store the result in=20
destination. Both <SPAN class=3Dsmallcode>aesimc</SPAN> and <SPAN=20
class=3Dsmallcode>vaesimc</SPAN> use only two operands, destination =
being SSE=20
register, and source being SSE register or 128-bit memory location. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>aeskeygenassist</SPAN> is a =
helper=20
instruction for generating the round key. It needs three operands: =
destination=20
being SSE register, source being SSE register or 128-bit memory, and =
third=20
operand being 8-bit immediate value. The AVX version of this instruction =
uses=20
the same syntax. </P>
<P class=3Dsmalltext>The CLMUL extension introduces just one =
instruction, <SPAN=20
class=3Dsmallcode>pclmulqdq</SPAN>, and its AVX version as well. This =
instruction=20
performs a carryless multiplication of two 64-bit values selected from =
first and=20
second source according to the bit fields in immediate value. The =
destination=20
and first source are SSE registers, second source is SSE register or =
128-bit=20
memory, and immediate value is provided as last operand. <SPAN=20
class=3Dsmallcode>vpclmulqdq</SPAN> takes four operands, while <SPAN=20
class=3Dsmallcode>pclmulqdq</SPAN> takes only three operands, with the =
first one=20
serving both the role of destination and first source. </P>
<P class=3Dsmalltext>The FMA (Fused Multiply-Add) extension introduces =
additional=20
AVX instructions which perform multiplication and summation as single =
operation.=20
Each one takes three operands, first one serving both the role of =
destination=20
and first source, and the following ones being the second and third =
source. The=20
mnemonic of FMA instruction is obtained by appending to <SPAN=20
class=3Dsmallcode>vf</SPAN> prefix: first either <SPAN =
class=3Dsmallcode>m</SPAN> or=20
<SPAN class=3Dsmallcode>nm</SPAN> to select whether result of =
multiplication=20
should be taken as-is or negated, then either <SPAN =
class=3Dsmallcode>add</SPAN>=20
or <SPAN class=3Dsmallcode>sub</SPAN> to select whether third value will =
be added=20
to the product or substracted from the product, then either <SPAN=20
class=3Dsmallcode>132</SPAN>, <SPAN class=3Dsmallcode>213</SPAN> or =
<SPAN=20
class=3Dsmallcode>231</SPAN> to select which source operands are =
multiplied and=20
which one is added or substracted, and finally the type of data on which =
the=20
instruction operates, either <SPAN class=3Dsmallcode>ps</SPAN>, <SPAN=20
class=3Dsmallcode>pd</SPAN>, <SPAN class=3Dsmallcode>ss</SPAN> or <SPAN=20
class=3Dsmallcode>sd</SPAN>. As it was with SSE instructions promoted to =
AVX,=20
instructions operating on packed floating point values allow 128-bit or =
256-bit=20
syntax, in former all the operands are SSE registers, but the third one =
can also=20
be a 128-bit memory, in latter the operands are AVX registers and the =
third one=20
can also be a 256-bit memory. Instructions that compute just one =
floating point=20
result need operands to be SSE registers, and the third operand can also =
be a=20
memory, either 32-bit for single precision or 64-bit for double =
precision. </P><PRE class=3Dsmallcode>    vfmsub231ps ymm1,ymm2,ymm3     =
; multiply and substract
    vfnmadd132sd xmm0,xmm5,[ebx]   ; multiply, negate and add
</PRE>
<P class=3Dsmalltext>In addition to the instructions created by the rule =
described=20
above, there are families of instructions with mnemonics starting with =
either=20
<SPAN class=3Dsmallcode>vfmaddsub</SPAN> or <SPAN=20
class=3Dsmallcode>vfmsubadd</SPAN>, followed by either <SPAN=20
class=3Dsmallcode>132</SPAN>, <SPAN class=3Dsmallcode>213</SPAN> or =
<SPAN=20
class=3Dsmallcode>231</SPAN> and then either <SPAN =
class=3Dsmallcode>ps</SPAN> or=20
<SPAN class=3Dsmallcode>pd</SPAN> (the operation must always be on =
packed values=20
in this case). They add to the result of multiplication or substract =
from it=20
depending on the position of value in packed data - instructions from =
the <SPAN=20
class=3Dsmallcode>vfmaddsub</SPAN> group add when the position is odd =
and=20
substract when the position is even, instructions from the <SPAN=20
class=3Dsmallcode>vfmsubadd</SPAN> group add when the position is even =
and=20
subtstract when the position is odd. The rules for operands are the same =
as for=20
other FMA instructions. </P>
<P class=3Dsmalltext>The FMA4 instructions are similar to FMA, but use =
syntax with=20
four operands and thus allow destination to be different than all the =
sources.=20
Their mnemonics are identical to FMA instructions with the <SPAN=20
class=3Dsmallcode>132</SPAN>, <SPAN class=3Dsmallcode>213</SPAN> or =
<SPAN=20
class=3Dsmallcode>231</SPAN> cut out, as having separate destination =
operand makes=20
such selection of operands superfluous. The multiplication is always =
performed=20
on values from the first and second source, and then the value from =
third source=20
is added or substracted. Either second or third source can be a memory =
operand,=20
and the rules for the sizes of operands are the same as for FMA =
instructions.=20
</P><PRE class=3Dsmallcode>    vfmaddpd ymm0,ymm1,[esi],ymm2  ; multiply =
and add
    vfmsubss xmm0,xmm1,xmm2,[ebx]  ; multiply and substract
</PRE>
<P class=3Dsmalltext>The F16C extension consists of two instructions, =
<SPAN=20
class=3Dsmallcode>vcvtps2ph</SPAN> and <SPAN =
class=3Dsmallcode>vcvtph2ps</SPAN>,=20
which convert floating point values between single precision and half =
precision=20
(the 16-bit floating point format). <SPAN =
class=3Dsmallcode>vcvtps2ph</SPAN> takes=20
three operands: destination, source, and rounding controls. The third =
operand is=20
always an immediate, the source is either SSE or AVX register containing =
single=20
precision values, and the destination is SSE register or memory, the =
size of=20
memory is 64 bits when the source is SSE register and 128 bits when the =
source=20
is AVX register. <SPAN class=3Dsmallcode>vcvtph2ps</SPAN> takes two =
operands, the=20
destination that can be SSE or AVX register, and the source that is SSE =
register=20
or memory with size of the half of destination operand's size. </P>
<P class=3Dsmalltext>The AMD XOP extension introduces a number of new =
vector=20
instructions with encoding and syntax analogous to AVX instructions. =
<SPAN=20
class=3Dsmallcode>vfrczps</SPAN>, <SPAN =
class=3Dsmallcode>vfrczss</SPAN>, <SPAN=20
class=3Dsmallcode>vfrczpd</SPAN> and <SPAN =
class=3Dsmallcode>vfrczsd</SPAN> extract=20
fractional portions of single or double precision values, they all take =
two=20
operands. The packed operations allow either SSE or AVX register as =
destination,=20
for the other two it has to be SSE register. Source can be register of =
the same=20
type as destination, or memory of appropriate size (256-bit for =
destination=20
being AVX register, 128-bit for packed operation with destination being =
SSE=20
register, 64-bit for operation on a solitary double precision value and =
32-bit=20
for operation on a solitary single precision value). </P><PRE =
class=3Dsmallcode>    vfrczps ymm0,[esi]           ; load fractional =
parts
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpcmov</SPAN> copies bits =
from either=20
first or second source into destination depending on the values of =
corresponding=20
bits in the fourth operand (the selector). If the bit in selector is =
set, the=20
corresponding bit from first source is copied into the same position in=20
destination, otherwise the bit from second source is copied. Either =
second=20
source or selector can be memory location, 128-bit or 256-bit depending =
on=20
whether SSE registers or AVX registers are specified as the other =
operands. </P><PRE class=3Dsmallcode>    vpcmov xmm0,xmm1,xmm2,[ebx]  ; =
selector in memory
    vpcmov ymm0,ymm5,[esi],ymm2  ; source in memory
</PRE>
<P class=3Dsmalltext>The family of packed comparison instructions take =
four=20
operands, the destination and first source being SSE register, second =
source=20
being SSE register or 128-bit memory and the fourth operand being =
immediate=20
value defining the type of comparison. The mnemonic or instruction is =
created by=20
appending to <SPAN class=3Dsmallcode>vpcom</SPAN> prefix either <SPAN=20
class=3Dsmallcode>b</SPAN> or <SPAN class=3Dsmallcode>ub</SPAN> to =
compare signed or=20
unsigned bytes, <SPAN class=3Dsmallcode>w</SPAN> or <SPAN=20
class=3Dsmallcode>uw</SPAN> to compare signed or unsigned words, <SPAN=20
class=3Dsmallcode>d</SPAN> or <SPAN class=3Dsmallcode>ud</SPAN> to =
compare signed or=20
unsigned double words, <SPAN class=3Dsmallcode>q</SPAN> or <SPAN=20
class=3Dsmallcode>uq</SPAN> to compare signed or unsigned quad words. =
The=20
respective values from the first and second source are compared and the=20
corresponding data element in destination is set to either all ones or =
all zeros=20
depending on the result of comparison. The fourth operand has to specify =
one of=20
the eight comparison types (table <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#_2.5">2.5</A>)=
. All these=20
instructions have also variants with only three operands and the type of =

comparison encoded within the instruction name by inserting the =
comparison=20
mnemonic after <SPAN class=3Dsmallcode>vpcom</SPAN>. </P><PRE =
class=3Dsmallcode>    vpcomb   xmm0,xmm1,xmm2,4    ; test for equal =
bytes
    vpcomgew xmm0,xmm1,[ebx]     ; compare signed words
</PRE>
<P class=3Dsmalltext><B><A name=3D_2.5>Table 2.5 XOP =
comparisons.</A></B> </P>
<TABLE style=3D"WIDTH: 350px" class=3Ddoctable>
  <TBODY>
  <TR>
    <TH>Code</TH>
    <TH>Mnemonic</TH>
    <TH>Description</TH></TR>
  <TR>
    <TD>0</TD>
    <TD><SPAN class=3Dsmallcode>lt</SPAN></TD>
    <TD>less than</TD></TR>
  <TR>
    <TD>1</TD>
    <TD><SPAN class=3Dsmallcode>le</SPAN></TD>
    <TD>less than or equal</TD></TR>
  <TR>
    <TD>2</TD>
    <TD><SPAN class=3Dsmallcode>gt</SPAN></TD>
    <TD>greater than</TD></TR>
  <TR>
    <TD>3</TD>
    <TD><SPAN class=3Dsmallcode>ge</SPAN></TD>
    <TD>greater than or equal</TD></TR>
  <TR>
    <TD>4</TD>
    <TD><SPAN class=3Dsmallcode>eq</SPAN></TD>
    <TD>equal</TD></TR>
  <TR>
    <TD>5</TD>
    <TD><SPAN class=3Dsmallcode>neq</SPAN></TD>
    <TD>not equal</TD></TR>
  <TR>
    <TD>6</TD>
    <TD><SPAN class=3Dsmallcode>false</SPAN></TD>
    <TD>false</TD></TR>
  <TR>
    <TD>7</TD>
    <TD><SPAN class=3Dsmallcode>true</SPAN></TD>
    <TD>true</TD></TR></TBODY></TABLE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpermil2ps</SPAN> and <SPAN =

class=3Dsmallcode>vpermil2pd</SPAN> set the elements in destination =
register to=20
zero or to a value selected from first or second source depending on the =

corresponding bit fields from the fourth operand (the selector) and the=20
immediate value provided in fifth operand. Refer to the AMD manuals for =
the=20
detailed explanation of the operation performed by these instructions. =
Each of=20
the first four operands can be a register, and either second source or =
selector=20
can be memory location, 128-bit or 256-bit depending on whether SSE =
registers or=20
AVX registers are used for the other operands. </P><PRE =
class=3Dsmallcode>    vpermil2ps ymm0,ymm3,ymm7,ymm2,0  ; permute from =
two sources
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vphaddbw</SPAN> adds pairs =
of adjacent=20
signed bytes to form 16-bit values and stores them at the same positions =
in=20
destination. <SPAN class=3Dsmallcode>vphaddubw</SPAN> does the same but =
treats the=20
bytes as unsigned. <SPAN class=3Dsmallcode>vphaddbd</SPAN> and <SPAN=20
class=3Dsmallcode>vphaddubd</SPAN> sum all bytes (either signed or =
unsigned) in=20
each four-byte block to 32-bit results, <SPAN =
class=3Dsmallcode>vphaddbq</SPAN>=20
and <SPAN class=3Dsmallcode>vphaddubq</SPAN> sum all bytes in each =
eight-byte=20
block to 64-bit results, <SPAN class=3Dsmallcode>vphaddwd</SPAN> and =
<SPAN=20
class=3Dsmallcode>vphadduwd</SPAN> add pairs of words to 32-bit results, =
<SPAN=20
class=3Dsmallcode>vphaddwq</SPAN> and <SPAN =
class=3Dsmallcode>vphadduwq</SPAN> sum=20
all words in each four-word block to 64-bit results, <SPAN=20
class=3Dsmallcode>vphadddq</SPAN> and <SPAN =
class=3Dsmallcode>vphaddudq</SPAN> add=20
pairs of double words to 64-bit results. <SPAN =
class=3Dsmallcode>vphsubbw</SPAN>=20
substracts in each two-byte block the byte at higher position from the =
one at=20
lower position, and stores the result as a signed 16-bit value at the=20
corresponding position in destination, <SPAN =
class=3Dsmallcode>vphsubwd</SPAN>=20
substracts in each two-word block the word at higher position from the =
one at=20
lower position and makes signed 32-bit results, <SPAN=20
class=3Dsmallcode>vphsubdq</SPAN> substract in each block of two double =
word the=20
one at higher position from the one at lower position and makes signed =
64-bit=20
results. Each of these instructions takes two operands, the destination =
being=20
SSE register, and the source being SSE register or 128-bit memory. =
</P><PRE class=3Dsmallcode>    vphadduwq xmm0,xmm1          ; sum =
quadruplets of words
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpmacsww</SPAN> and <SPAN=20
class=3Dsmallcode>vpmacssww</SPAN> multiply the corresponding signed =
16-bit values=20
from the first and second source and then add the products to the =
parallel=20
values from the third source, then <SPAN =
class=3Dsmallcode>vpmacsww</SPAN> takes=20
the lowest 16 bits of the result and <SPAN =
class=3Dsmallcode>vpmacssww</SPAN>=20
saturates the result down to 16-bit value, and they store the final =
16-bit=20
results in the destination. <SPAN class=3Dsmallcode>vpmacsdd</SPAN> and =
<SPAN=20
class=3Dsmallcode>vpmacssdd</SPAN> perform the analogous operation on =
32-bit=20
values. <SPAN class=3Dsmallcode>vpmacswd</SPAN> and <SPAN=20
class=3Dsmallcode>vpmacsswd</SPAN> do the same calculation only on the =
low 16-bit=20
values from each 32-bit block and form the 32-bit results. <SPAN=20
class=3Dsmallcode>vpmacsdql</SPAN> and <SPAN =
class=3Dsmallcode>vpmacssdql</SPAN>=20
perform such operation on the low 32-bit values from each 64-bit block =
and form=20
the 64-bit results, while <SPAN class=3Dsmallcode>vpmacsdqh</SPAN> and =
<SPAN=20
class=3Dsmallcode>vpmacssdqh</SPAN> do the same on the high 32-bit =
values from=20
each 64-bit block, also forming the 64-bit results. <SPAN=20
class=3Dsmallcode>vpmadcswd</SPAN> and <SPAN =
class=3Dsmallcode>vpmadcsswd</SPAN>=20
multiply the corresponding signed 16-bit value from the first and second =
source,=20
then sum all the four products and add this sum to each 16-bit element =
from=20
third source, storing the truncated or saturated result in destination. =
All=20
these instructions take four operands, the second source can be 128-bit =
memory=20
or SSE register, all the other operands have to be SSE registers. =
</P><PRE class=3Dsmallcode>    vpmacsdd xmm6,xmm1,[ebx],xmm6  ; =
accumulate product
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpperm</SPAN> selects bytes =
from first=20
and second source, optionally applies a separate transformation to each =
of them,=20
and stores them in the destination. The bit fields in fourth operand =
(the=20
selector) specify for each position in destination what byte from which =
source=20
is taken and what operation is applied to it before it is stored there. =
Refer to=20
the AMD manuals for the detailed information about these bit fields. =
This=20
instruction takes four operands, either second source or selector can be =
a=20
128-bit memory (or they can be SSE registers both), all the other =
operands have=20
to be SSE registers. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpshlb</SPAN>, <SPAN=20
class=3Dsmallcode>vpshlw</SPAN>, <SPAN class=3Dsmallcode>vpshld</SPAN> =
and <SPAN=20
class=3Dsmallcode>vpshlq</SPAN> shift logically bytes, words, double =
words or quad=20
words respectively. The amount of bits to shift by is specified for each =
element=20
separately by the signed byte placed at the corresponding position in =
the third=20
operand. The source containing elements to shift is provided as second =
operand.=20
Either second or third operand can be 128-bit memory (or they can be SSE =

registers both) and the other operands have to be SSE registers. =
</P><PRE class=3Dsmallcode>    vpshld xmm3,xmm1,[ebx]       ; shift =
bytes from xmm1
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vpshab</SPAN>, <SPAN=20
class=3Dsmallcode>vpshaw</SPAN>, <SPAN class=3Dsmallcode>vpshad</SPAN> =
and <SPAN=20
class=3Dsmallcode>vpshaq</SPAN> arithmetically shift bytes, words, =
double words or=20
quad words. These instructions follow the same rules as the logical =
shifts=20
described above. <SPAN class=3Dsmallcode>vprotb</SPAN>, <SPAN=20
class=3Dsmallcode>vprotw</SPAN>, <SPAN class=3Dsmallcode>vprotd</SPAN> =
and <SPAN=20
class=3Dsmallcode>vprotq</SPAN> rotate bytes, word, double words or quad =
words.=20
They follow the same rules as shifts, but additionally allow third =
operand to be=20
immediate value, in which case the same amount of rotation is specified =
for all=20
the elements in source. </P><PRE class=3Dsmallcode>    vprotb =
xmm0,[esi],3          ; rotate bytes to the left
</PRE>
<P class=3Dsmalltext>The MOVBE extension introduces just one new =
instruction,=20
<SPAN class=3Dsmallcode>movbe</SPAN>, which swaps bytes in value from =
source=20
before storing it in destination, so can be used to load and store big =
endian=20
values. It takes two operands, either the destination or source should =
be a=20
16-bit, 32-bit or 64-bit memory (the last one being only allowed in long =
mode),=20
and the other operand should be a general register of the same size. =
</P>
<P class=3Dsmalltext>The BMI extension, consisting of two subsets - BMI1 =
and BMI2,=20
introduces new instructions operating on general registers, which use =
the same=20
encoding as AVX instructions and so allow the extended syntax. All these =

instructions use 32-bit operands, and in long mode they also allow the =
forms=20
with 64-bit operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>andn</SPAN> calculates the =
bitwise AND=20
of second source with the inverted bits of first source and stores the =
result in=20
destination. The destination and the first source have to be general =
registers,=20
the second source can be general register or memory. </P><PRE =
class=3Dsmallcode>    andn edx,eax,[ebx]   ; bit-multiply inverted eax =
with memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bextr</SPAN> extracts from =
the first=20
source the sequence of bits using an index and length specified by bit =
fields in=20
the second source operand and stores it into destination. The lowest 8 =
bits of=20
second source specify the position of bit sequence to extract and the =
next 8=20
bits of second source specify the length of sequence. The first source =
can be a=20
general register or memory, the other two operands have to be general =
registers.=20
</P><PRE class=3Dsmallcode>    bextr eax,[esi],ecx  ; extract bit field =
from memory
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>blsi</SPAN> extracts the =
lowest set bit=20
from the source, setting all the other bits in destination to zero. The=20
destination must be a general register, the source can be general =
register or=20
memory. </P><PRE class=3Dsmallcode>    blsi rax,r11         ; isolate =
the lowest set bit
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>blsmsk</SPAN> sets all the =
bits in the=20
destination up to the lowest set bit in the source, including this bit. =
<SPAN=20
class=3Dsmallcode>blsr</SPAN> copies all the bits from the source to =
destination=20
except for the lowest set bit, which is replaced by zero. These =
instructions=20
follow the same rules for operands as <SPAN =
class=3Dsmallcode>blsi</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>tzcnt</SPAN> counts the =
number of=20
trailing zero bits, that is the zero bits up to the lowest set bit of =
source=20
value. This instruction is analogous to <SPAN =
class=3Dsmallcode>lzcnt</SPAN> and=20
follows the same rules for operands, so it also has a 16-bit version, =
unlike the=20
other BMI instructions. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>bzhi</SPAN> is BMI2 =
instruction, which=20
copies the bits from first source to destination, zeroing all the bits =
up from=20
the position specified by second source. It follows the same rules for =
operands=20
as <SPAN class=3Dsmallcode>bextr</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>pext</SPAN> uses a mask in =
second=20
source operand to select bits from first operands and puts the selected =
bits as=20
a continuous sequence into destination. <SPAN =
class=3Dsmallcode>pdep</SPAN>=20
performs the reverse operation - it takes sequence of bits from the =
first source=20
and puts them consecutively at the positions where the bits in second =
source are=20
set, setting all the other bits in destination to zero. These BMI2 =
instructions=20
follow the same rules for operands as <SPAN =
class=3Dsmallcode>andn</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>mulx</SPAN> is a BMI2 =
instruction which=20
performs an unsigned multiplication of value from EDX or RDX register =
(depending=20
on the size of specified operands) by the value from third operand, and =
stores=20
the low half of result in the second operand, and the high half of =
result in the=20
first operand, and it does it without affecting the flags. The third =
operand can=20
be general register or memory, and both the destination operands have to =
be=20
general registers. </P><PRE class=3Dsmallcode>    mulx edx,eax,ecx     ; =
multiply edx by ecx into edx:eax
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>shlx</SPAN>, <SPAN=20
class=3Dsmallcode>shrx</SPAN> and <SPAN class=3Dsmallcode>sarx</SPAN> =
are BMI2=20
instructions, which perform logical or arithmetical shifts of value from =
first=20
source by the amount specified by second source, and store the result in =

destination without affecting the flags. The have the same rules for =
operands as=20
<SPAN class=3Dsmallcode>bzhi</SPAN> instruction. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>rorx</SPAN> is a BMI2 =
instruction which=20
rotates right the value from source operand by the constant amount =
specified in=20
third operand and stores the result in destination without affecting the =
flags.=20
The destination operand has to be general register, the source operand =
can be=20
general register or memory, and the third operand has to be an immediate =
value.=20
</P><PRE class=3Dsmallcode>    rorx eax,edx,7       ; rotate without =
affecting flags
</PRE>
<P class=3Dsmalltext>The TBM is an extension designed by AMD to =
supplement the BMI=20
set. The <SPAN class=3Dsmallcode>bextr</SPAN> instruction is extended =
with a new=20
form, in which second source is a 32-bit immediate value. <SPAN=20
class=3Dsmallcode>blsic</SPAN> is a new instruction which performs the =
same=20
operation as <SPAN class=3Dsmallcode>blsi</SPAN>, but with the bits of =
result=20
reversed. It uses the same rules for operands as <SPAN=20
class=3Dsmallcode>blsi</SPAN>. <SPAN class=3Dsmallcode>blsfill</SPAN> is =
a new=20
instruction, which takes the value from source, sets all the bits below =
the=20
lowest set bit and store the result in destination, it also uses the =
same rules=20
for operands as <SPAN class=3Dsmallcode>blsi</SPAN>. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>blci</SPAN>, <SPAN=20
class=3Dsmallcode>blcic</SPAN>, <SPAN class=3Dsmallcode>blcs</SPAN>, =
<SPAN=20
class=3Dsmallcode>blcmsk</SPAN> and <SPAN =
class=3Dsmallcode>blcfill</SPAN> are=20
instructions analogous to <SPAN class=3Dsmallcode>blsi</SPAN>, <SPAN=20
class=3Dsmallcode>blsic</SPAN>, <SPAN class=3Dsmallcode>blsr</SPAN>, =
<SPAN=20
class=3Dsmallcode>blsmsk</SPAN> and <SPAN =
class=3Dsmallcode>blsfill</SPAN>=20
respectively, but they perform the bit-inverted versions of the same =
operations.=20
They follow the same rules for operands as the instructions they =
reflect. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>tzmsk</SPAN> finds the =
lowest set bit=20
in value from source operand, sets all bits below it to 1 and all the =
rest of=20
bits to zero, then writes the result to destination. <SPAN=20
class=3Dsmallcode>t1mskc</SPAN> finds the least significant zero bit in =
the value=20
from source operand, sets the bits below it to zero and all the other =
bits to 1,=20
and writes the result to destination. These instructions have the same =
rules for=20
operands as <SPAN class=3Dsmallcode>blsi</SPAN>. </P>
<P><B><A class=3Dsmalltext name=3D2.1.24>2.1.24 Other extensions of =
instruction=20
set</A> </B></P>
<P class=3Dsmalltext>There is a number of additional instruction set =
extensions=20
recognized by flat assembler, and the general syntax of the instructions =

introduced by those extensions is provided here. For a detailed =
information on=20
the operations performed by them, check out the manuals from Intel (for =
the VMX,=20
SMX, XSAVE, RDRAND, FSGSBASE, INVPCID, HLE and RTM extensions) or AMD =
(for the=20
SVM extension). </P>
<P class=3Dsmalltext>The Virtual-Machine Extensions (VMX) provide a set =
of=20
instructions for the management of virtual machines. The <SPAN=20
class=3Dsmallcode>vmxon</SPAN> instruction, which enters the VMX =
operation,=20
requires a single 64-bit memory operand, which should be a physical =
address of=20
memory region, which the logical processor may use to support VMX =
operation. The=20
<SPAN class=3Dsmallcode>vmxoff</SPAN> instruction, which leaves the VMX =
operation,=20
has no operands. The <SPAN class=3Dsmallcode>vmlaunch</SPAN> and <SPAN=20
class=3Dsmallcode>vmresume</SPAN>, which launch or resume the virtual =
machines,=20
and <SPAN class=3Dsmallcode>vmcall</SPAN>, which allows guest software =
to call the=20
VM monitor, use no operands either. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>vmptrld</SPAN> loads =
the physical=20
address of current Virtual Machine Control Structure (VMCS) from its =
memory=20
operand, <SPAN class=3Dsmallcode>vmptrst</SPAN> stores the pointer to =
current VMCS=20
into address specified by its memory operand, and <SPAN=20
class=3Dsmallcode>vmclear</SPAN> sets the launch state of the VMCS =
referenced by=20
its memory operand to clear. These three instruction all require single =
64-bit=20
memory operand. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>vmread</SPAN> reads =
from VCMS a=20
field specified by the source operand and stores it into the destination =

operand. The source operand should be a general purpose register, and =
the=20
destination operand can be a register of memory. The <SPAN=20
class=3Dsmallcode>vmwrite</SPAN> writes into a VMCS field specified by =
the=20
destination operand the value provided by source operand. The source =
operand can=20
be a general purpose register or memory, and the destination operand =
must be a=20
register. The size of operands for those instructions should be 64-bit =
when in=20
long mode, and 32-bit otherwise. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>invept</SPAN> and <SPAN =

class=3Dsmallcode>invvpid</SPAN> invalidate the translation lookaside =
buffers=20
(TLBs) and paging-structure caches, either derived from extended page =
tables=20
(EPT), or based on the virtual processor identifier (VPID). These =
instructions=20
require two operands, the first one being the general purpose register=20
specifying the type of invalidation, and the second one being a 128-bit =
memory=20
operand providing the invalidation descriptor. The first operand should =
be a=20
64-bit register when in long mode, and 32-bit register otherwise. </P>
<P class=3Dsmalltext>The Safer Mode Extensions (SMX) provide the =
functionalities=20
available throught the <SPAN class=3Dsmallcode>getsec</SPAN> =
instruction. This=20
instruction takes no operands, and the function that is executed is =
determined=20
by the contents of EAX register upon executing this instruction. </P>
<P class=3Dsmalltext>The Secure Virtual Machine (SVM) is a variant of =
virtual=20
machine extension used by AMD. The <SPAN class=3Dsmallcode>skinit</SPAN> =

instruction securely reinitializes the processor allowing the startup of =
trusted=20
software, such as the virtual machine monitor (VMM). This instruction =
takes a=20
single operand, which must be EAX, and provides a physical address of =
the secure=20
loader block (SLB). </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>vmrun</SPAN> =
instruction is used to=20
start a guest virtual machine, its only operand should be an accumulator =

register (AX, EAX or RAX, the last one available only in long mode) =
providing=20
the physical address of the virtual machine control block (VMCB). The =
<SPAN=20
class=3Dsmallcode>vmsave</SPAN> stores a subset of processor state into =
VMCB=20
specified by its operand, and <SPAN class=3Dsmallcode>vmload</SPAN> =
loads the same=20
subset of processor state from a specified VMCB. The same operand rules =
as for=20
the <SPAN class=3Dsmallcode>vmrun</SPAN> apply to those two =
instructions. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>vmmcall</SPAN> allows the =
guest=20
software to call the VMM. This instruction takes no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>stgi</SPAN> set the global =
interrupt=20
flag to 1, and <SPAN class=3Dsmallcode>clgi</SPAN> zeroes it. These =
instructions=20
take no operands. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>invlpga</SPAN> invalidates =
the TLB=20
mapping for a virtual page specified by the first operand (which has to =
be=20
accumulator register) and address space identifier specified by the =
second=20
operand (which must be ECX register). </P>
<P class=3Dsmalltext>The XSAVE set of instructions allows to save and =
restore=20
processor state components. <SPAN class=3Dsmallcode>xsave</SPAN> and =
<SPAN=20
class=3Dsmallcode>xsaveopt</SPAN> store the components of processor =
state defined=20
by bit mask in EDX and EAX registers into area defined by memory =
operand. <SPAN=20
class=3Dsmallcode>xrstor</SPAN> restores from the area specified by =
memory operand=20
the components of processor state defined by mask in EDX and EAX. The =
<SPAN=20
class=3Dsmallcode>xsave64</SPAN>, <SPAN =
class=3Dsmallcode>xsaveopt64</SPAN> and=20
<SPAN class=3Dsmallcode>xrstor64</SPAN> are 64-bit versions of these =
instructions,=20
allowed only in long mode. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>xgetbv</SPAN> read the =
contents of=20
64-bit XCR (extended control register) specified in ECX register into =
EDX and=20
EAX registers. <SPAN class=3Dsmallcode>xsetbv</SPAN> writes the contents =
of EDX=20
and EAX into the 64-bit XCR specified by ECX register. These =
instructions have=20
no operands. </P>
<P class=3Dsmalltext>The RDRAND extension introduces one new =
instruction, <SPAN=20
class=3Dsmallcode>rdrand</SPAN>, which loads the hardware-generated =
random value=20
into general register. It takes one operand, which can be 16-bit, 32-bit =
or=20
64-bit register (with the last one being allowed only in long mode). =
</P>
<P class=3Dsmalltext>The FSGSBASE extension adds long mode instructions =
that allow=20
to read and write the segment base registers for FS and GS segments. =
<SPAN=20
class=3Dsmallcode>rdfsbase</SPAN> and <SPAN =
class=3Dsmallcode>rdgsbase</SPAN> read=20
the corresponding segment base registers into operand, while <SPAN=20
class=3Dsmallcode>wrfsbase</SPAN> and <SPAN =
class=3Dsmallcode>wrgsbase</SPAN> write=20
the value of operand into those register. All these instructions take =
one=20
operand, which can be 32-bit or 64-bit general register. </P>
<P class=3Dsmalltext>The INVPCID extension adds <SPAN=20
class=3Dsmallcode>invpcid</SPAN> instruction, which invalidates mapping =
in the=20
TLBs and paging caches based on the invalidation type specified in first =
operand=20
and PCID invalidate descriptor specified in second operand. The first =
operands=20
should be 32-bit general register when not in long mode, or 64-bit =
general=20
register when in long mode. The second operand should be 128-bit memory=20
location. </P>
<P class=3Dsmalltext>The HLE and RTM extensions provide set of =
instructions for=20
the transactional management. The <SPAN =
class=3Dsmallcode>xacquire</SPAN> and=20
<SPAN class=3Dsmallcode>xrelease</SPAN> are new prefixes that can be =
used with=20
some of the instructions to start or end lock elision on the memory =
address=20
specified by prefixed instruction. The <SPAN =
class=3Dsmallcode>xbegin</SPAN>=20
instruction starts the transactional execution, its operand is the =
address a=20
fallback routine that gets executes in case of transaction abort, =
specified like=20
the operand for near jump instruction. <SPAN =
class=3Dsmallcode>xend</SPAN> marks=20
the end of transcational execution region, it takes no operands. <SPAN=20
class=3Dsmallcode>xabort</SPAN> forces the transaction abort, it takes =
an 8-bit=20
immediate value as its only operand, this value is passed in the highest =
bits of=20
EAX to the fallback routine. <SPAN class=3Dsmallcode>xtest</SPAN> checks =
whether=20
there is transactional execution in progress, this instruction takes no=20
operands. </P>
<P><B><A class=3Dmediumtext name=3D2.2>2.2 Control directives</A> =
</B></P>
<P class=3Dsmalltext>This section describes the directives that control =
the=20
assembly process, they are processed during the assembly and may cause =
some=20
blocks of instructions to be assembled differently or not assembled at =
all. </P>
<P><B><A class=3Dsmalltext name=3D2.2.1>2.2.1 Numerical constants</A> =
</B></P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>=3D</SPAN> directive =
allows to define=20
the numerical constant. It should be preceded by the name for the =
constant and=20
followed by the numerical expression providing the value. The value of =
such=20
constants can be a number or an address, but - unlike labels - the =
numerical=20
constants are not allowed to hold the register-based addresses. Besides =
this=20
difference, in their basic variant numerical constants behave very much =
like=20
labels and you can even forward-reference them (access their values =
before they=20
actually get defined). </P>
<P class=3Dsmalltext>There is, however, a second variant of numerical =
constants,=20
which is recognized by assembler when you try to define the constant of =
name,=20
under which there already was a numerical constant defined. In such case =

assembler treats that constant as an assembly-time variable and allows =
it to be=20
assigned with new value, but forbids forward-referencing it (for obvious =

reasons). Let's see both the variant of numerical constants in one =
example: </P><PRE class=3Dsmallcode>    dd sum
    x =3D 1
    x =3D x+2
    sum =3D x
</PRE>
<P class=3Dsmalltext>Here the <SPAN class=3Dsmallcode>x</SPAN> is an =
assembly-time=20
variable, and every time it is accessed, the value that was assigned to =
it the=20
most recently is used. Thus if we tried to access the <SPAN=20
class=3Dsmallcode>x</SPAN> before it gets defined the first time, like =
if we wrote=20
<SPAN class=3Dsmallcode>dd&nbsp;x</SPAN> in place of the <SPAN=20
class=3Dsmallcode>dd&nbsp;sum</SPAN> instruction, it would cause an =
error. And=20
when it is re-defined with the <SPAN =
class=3Dsmallcode>x&nbsp;=3D&nbsp;x+2</SPAN>=20
directive, the previous value of <SPAN class=3Dsmallcode>x</SPAN> is =
used to=20
calculate the new one. So when the <SPAN class=3Dsmallcode>sum</SPAN> =
constant=20
gets defined, the <SPAN class=3Dsmallcode>x</SPAN> has value of 3, and =
this value=20
is assigned to the <SPAN class=3Dsmallcode>sum</SPAN>. Since this one is =
defined=20
only once in source, it is the standard numerical constant, and can be=20
forward-referenced. So the <SPAN class=3Dsmallcode>dd&nbsp;sum</SPAN> is =
assembled=20
as <SPAN class=3Dsmallcode>dd&nbsp;3</SPAN>. To read more about how the =
assembler=20
is able to resolve this, see section <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.6">2.2.6</=
A>. </P>
<P class=3Dsmalltext>The value of numerical constant can be preceded by =
size=20
operator, which can ensure that the value will fit in the range for the=20
specified size, and can affect also how some of the calculations inside =
the=20
numerical expression are performed. This example: </P><PRE =
class=3Dsmallcode>    c8 =3D byte -1
    c32 =3D dword -1
</PRE>
<P class=3Dsmalltext>defines two different constants, the first one fits =
in 8=20
bits, the second one fits in 32 bits. </P>
<P class=3Dsmalltext>When you need to define constant with the value of =
address,=20
which may be register-based (and thus you cannot employ numerical =
constant for=20
this purpose), you can use the extended syntax of <SPAN=20
class=3Dsmallcode>label</SPAN> directive (already described in section =
<A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#1.2.3">1.2.3</=
A>), like:=20
</P><PRE class=3Dsmallcode>    label myaddr at ebp+4
</PRE>
<P class=3Dsmalltext>which declares label placed at <SPAN=20
class=3Dsmallcode>ebp+4</SPAN> address. However remember that labels, =
unlike=20
numerical constants, cannot become assembly-time variables. </P>
<P><B><A class=3Dsmalltext name=3D2.2.2>2.2.2 Conditional assembly</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>if</SPAN> directive causes =
come block=20
of instructions to be assembled only under certain condition. It should =
be=20
followed by logical expression specifying the condition, instructions in =
next=20
lines will be assembled only when this condition is met, otherwise they =
will be=20
skipped. The optional <SPAN class=3Dsmallcode>else&nbsp;if</SPAN> =
directive=20
followed with logical expression specifying additional condition begins =
the next=20
block of instructions that will be assembled if previous conditions were =
not=20
met, and the additional condition is met. The optional <SPAN=20
class=3Dsmallcode>else</SPAN> directive begins the block of instructions =
that will=20
be assembled if all the conditions were not met. The <SPAN=20
class=3Dsmallcode>end&nbsp;if</SPAN> directive ends the last block of=20
instructions. </P>
<P class=3Dsmalltext>You should note that <SPAN =
class=3Dsmallcode>if</SPAN>=20
directive is processed at assembly stage and therefore it doesn't affect =
any=20
preprocessor directives, like the definitions of symbolic constants and=20
macroinstructions - when the assembler recognizes the <SPAN=20
class=3Dsmallcode>if</SPAN> directive, all the preprocessing has been =
already=20
finished. </P>
<P class=3Dsmalltext>The logical expression consist of logical values =
and logical=20
operators. The logical operators are <SPAN class=3Dsmallcode>~</SPAN> =
for logical=20
negation, <SPAN class=3Dsmallcode>&amp;</SPAN> for logical and, <SPAN=20
class=3Dsmallcode>|</SPAN> for logical or. The negation has the highest =
priority.=20
Logical value can be a numerical expression, it will be false if it is =
equal to=20
zero, otherwise it will be true. Two numerical expression can be =
compared using=20
one of the following operators to make the logical value: <SPAN=20
class=3Dsmallcode>=3D</SPAN> (equal), <SPAN =
class=3Dsmallcode>&lt;</SPAN> (less),=20
<SPAN class=3Dsmallcode>&gt;</SPAN> (greater), <SPAN =
class=3Dsmallcode>&lt;=3D</SPAN>=20
(less or equal), <SPAN class=3Dsmallcode>&gt;=3D</SPAN> (greater or =
equal), <SPAN=20
class=3Dsmallcode>&lt;&gt;</SPAN> (not equal). </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>used</SPAN> operator =
followed by a=20
symbol name, is the logical value that checks whether the given symbol =
is used=20
somewhere (it returns correct result even if symbol is used only after =
this=20
check). The <SPAN class=3Dsmallcode>defined</SPAN> operator can be =
followed by any=20
expression, usually just by a single symbol name; it checks whether the =
given=20
expression contains only symbols that are defined in the source and =
accessible=20
from the current position. </P>
<P class=3Dsmalltext>With <SPAN class=3Dsmallcode>relativeto</SPAN> =
operator it is=20
possible to check whether values of two expressions differ only by =
constant=20
amount. The valid syntax is a numerical expression followed by <SPAN=20
class=3Dsmallcode>relativeto</SPAN> and then another expression =
(possibly=20
register-based). Labels that have no simple numerical value can be =
tested this=20
way to determine what kind of operations may be possible with them. </P>
<P class=3Dsmalltext>The following simple example uses the <SPAN=20
class=3Dsmallcode>count</SPAN> constant that should be defined somewhere =
in=20
source: </P><PRE class=3Dsmallcode>    if count&gt;0
        mov cx,count
        rep movsb
    end if
</PRE>
<P class=3Dsmalltext>These two assembly instructions will be assembled =
only if the=20
<SPAN class=3Dsmallcode>count</SPAN> constant is greater than 0. The =
next sample=20
shows more complex conditional structure: </P><PRE class=3Dsmallcode>    =
if count &amp; ~ count mod 4
        mov cx,count/4
        rep movsd
    else if count&gt;4
        mov cx,count/4
        rep movsd
        mov cx,count mod 4
        rep movsb
    else
        mov cx,count
        rep movsb
    end if
</PRE>
<P class=3Dsmalltext>The first block of instructions gets assembled when =
the <SPAN=20
class=3Dsmallcode>count</SPAN> is non zero and divisible by four, if =
this=20
condition is not met, the second logical expression, which follows the =
<SPAN=20
class=3Dsmallcode>else&nbsp;if</SPAN>, is evaluated and if it's true, =
the second=20
block of instructions get assembled, otherwise the last block of =
instructions,=20
which follows the line containing only <SPAN =
class=3Dsmallcode>else</SPAN>, is=20
assembled. </P>
<P class=3Dsmalltext>There are also operators that allow comparison of =
values=20
being any chains of symbols. The <SPAN class=3Dsmallcode>eq</SPAN> =
compares=20
whether two such values are exactly the same. The <SPAN=20
class=3Dsmallcode>in</SPAN> operator checks whether given value is a =
member of the=20
list of values following this operator, the list should be enclosed =
between=20
<SPAN class=3Dsmallcode>&lt;</SPAN> and <SPAN =
class=3Dsmallcode>&gt;</SPAN>=20
characters, its members should be separated with commas. The symbols are =

considered the same when they have the same meaning for the assembler - =
for=20
example <SPAN class=3Dsmallcode>pword</SPAN> and <SPAN=20
class=3Dsmallcode>fword</SPAN> for assembler are the same and thus are =
not=20
distinguished by the above operators. In the same way <SPAN=20
class=3Dsmallcode>16&nbsp;eq&nbsp;10h</SPAN> is the true condition, =
however <SPAN=20
class=3Dsmallcode>16&nbsp;eq&nbsp;10+4</SPAN> is not. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>eqtype</SPAN> operator =
checks=20
whether the two compared values have the same structure, and whether the =

structural elements are of the same type. The distinguished types =
include=20
numerical expressions, individual quoted strings, floating point =
numbers,=20
address expressions (the expressions enclosed in square brackets or =
preceded by=20
<SPAN class=3Dsmallcode>ptr</SPAN> operator), instruction mnemonics, =
registers,=20
size operators, jump type and code type operators. And each of the =
special=20
characters that act as a separators, like comma or colon, is the =
separate type=20
itself. For example, two values, each one consisting of register name =
followed=20
by comma and numerical expression, will be regarded as of the same type, =
no=20
matter what kind of register and how complicated numerical expression is =
used;=20
with exception for the quoted strings and floating point values, which =
are the=20
special kinds of numerical expressions and are treated as different =
types. Thus=20
<SPAN class=3Dsmallcode>eax,16&nbsp;eqtype&nbsp;fs,3+7</SPAN> condition =
is true,=20
but <SPAN class=3Dsmallcode>eax,16&nbsp;eqtype&nbsp;eax,1.6</SPAN> is =
false. </P>
<P><B><A class=3Dsmalltext name=3D2.2.3>2.2.3 Repeating blocks of =
instructions</A>=20
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>times</SPAN> directive =
repeats one=20
instruction specified number of times. It should be followed by =
numerical=20
expression specifying number of repeats and the instruction to repeat=20
(optionally colon can be used to separate number and instruction). When =
special=20
symbol <SPAN class=3Dsmallcode>%</SPAN> is used inside the instruction, =
it is=20
equal to the number of current repeat. For example <SPAN=20
class=3Dsmallcode>times&nbsp;5&nbsp;db&nbsp;%</SPAN> will define five =
bytes with=20
values 1, 2, 3, 4, 5. Recursive use of <SPAN =
class=3Dsmallcode>times</SPAN>=20
directive is also allowed, so <SPAN=20
class=3Dsmallcode>times&nbsp;3&nbsp;times&nbsp;%&nbsp;db&nbsp;%</SPAN> =
will define=20
six bytes with values 1, 1, 2, 1, 2, 3. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>repeat</SPAN> directive =
repeats the=20
whole block of instructions. It should be followed by numerical =
expression=20
specifying number of repeats. Instructions to repeat are expected in =
next lines,=20
ended with the <SPAN class=3Dsmallcode>end&nbsp;repeat</SPAN> directive, =
for=20
example: </P><PRE class=3Dsmallcode>    repeat 8
        mov byte [bx],%
        inc bx
    end repeat
</PRE>
<P class=3Dsmalltext>The generated code will store byte values from one =
to eight=20
in the memory addressed by BX register. </P>
<P class=3Dsmalltext>Number of repeats can be zero, in that case the =
instructions=20
are not assembled at all. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>break</SPAN> directive =
allows to=20
stop repeating earlier and continue assembly from the first line after =
the <SPAN=20
class=3Dsmallcode>end repeat</SPAN>. Combined with the <SPAN=20
class=3Dsmallcode>if</SPAN> directive it allows to stop repeating under =
some=20
special condition, like: </P><PRE class=3Dsmallcode>    s =3D x/2
    repeat 100
        if x/s =3D s
            break
        end if
        s =3D (s+x/s)/2
    end repeat
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>while</SPAN> directive =
repeats the=20
block of instructions as long as the condition specified by the logical=20
expression following it is true. The block of instructions to be =
repeated should=20
end with the <SPAN class=3Dsmallcode>end&nbsp;while</SPAN> directive. =
Before each=20
repetition the logical expression is evaluated and when its value is =
false, the=20
assembly is continued starting from the first line after the <SPAN=20
class=3Dsmallcode>end&nbsp;while</SPAN>. Also in this case the <SPAN=20
class=3Dsmallcode>%</SPAN> symbol holds the number of current repeat. =
The <SPAN=20
class=3Dsmallcode>break</SPAN> directive can be used to stop this kind =
of loop in=20
the same way as with <SPAN class=3Dsmallcode>repeat</SPAN> directive. =
The previous=20
sample can be rewritten to use the <SPAN class=3Dsmallcode>while</SPAN> =
instead of=20
<SPAN class=3Dsmallcode>repeat</SPAN> this way: </P><PRE =
class=3Dsmallcode>    s =3D x/2
    while x/s &lt;&gt; s
        s =3D (s+x/s)/2
        if % =3D 100
            break
        end if
    end while
</PRE>
<P class=3Dsmalltext>The blocks defined with <SPAN =
class=3Dsmallcode>if</SPAN>,=20
<SPAN class=3Dsmallcode>repeat</SPAN> and <SPAN =
class=3Dsmallcode>while</SPAN> can=20
be nested in any order, however they should be closed in the same order =
in which=20
they were started. The <SPAN class=3Dsmallcode>break</SPAN> directive =
always stops=20
processing the block that was started last with either the <SPAN=20
class=3Dsmallcode>repeat</SPAN> or <SPAN class=3Dsmallcode>while</SPAN> =
directive.=20
</P>
<P><B><A class=3Dsmalltext name=3D2.2.4>2.2.4 Addressing spaces</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>org</SPAN> directive sets =
address at=20
which the following code is expected to appear in memory. It should be =
followed=20
by numerical expression specifying the address. This directive begins =
the new=20
addressing space, the following code itself is not moved in any way, but =
all the=20
labels defined within it and the value of <SPAN =
class=3Dsmallcode>$</SPAN> symbol=20
are affected as if it was put at the given address. However it's the=20
responsibility of programmer to put the code at correct address at =
run-time.=20
</P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>load</SPAN> directive =
allows to=20
define constant with a binary value loaded from the already assembled =
code. This=20
directive should be followed by the name of the constant, then =
optionally size=20
operator, then <SPAN class=3Dsmallcode>from</SPAN> operator and a =
numerical=20
expression specifying a valid address in current addressing space. The =
size=20
operator has unusual meaning in this case - it states how many bytes (up =
to 8)=20
have to be loaded to form the binary value of constant. If no size =
operator is=20
specified, one byte is loaded (thus value is in range from 0 to 255). =
The loaded=20
data cannot exceed current offset. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>store</SPAN> directive =
can modify=20
the already generated code by replacing some of the previously generated =
data=20
with the value defined by given numerical expression, which follows. The =

expression can be preceded by the optional size operator to specify how =
large=20
value the expression defines, and therefore how much bytes will be =
stored, if=20
there is no size operator, the size of one byte is assumed. Then the =
<SPAN=20
class=3Dsmallcode>at</SPAN> operator and the numerical expression =
defining the=20
valid address in current addressing code space, at which the given value =
have to=20
be stored should follow. This is a directive for advanced appliances and =
should=20
be used carefully. </P>
<P class=3Dsmalltext>Both <SPAN class=3Dsmallcode>load</SPAN> and <SPAN=20
class=3Dsmallcode>store</SPAN> directives are limited to operate on =
places in=20
current addressing space. The <SPAN class=3Dsmallcode>$$</SPAN> symbol =
is always=20
equal to the base address of current addressing space, and the <SPAN=20
class=3Dsmallcode>$</SPAN> symbol is the address of current position in =
that=20
addressing space, therefore these two values define limits of the area, =
where=20
<SPAN class=3Dsmallcode>load</SPAN> and <SPAN =
class=3Dsmallcode>store</SPAN> can=20
operate. </P>
<P class=3Dsmalltext>Combining the <SPAN class=3Dsmallcode>load</SPAN> =
and <SPAN=20
class=3Dsmallcode>store</SPAN> directives allows to do things like =
encoding some=20
of the already generated code. For example to encode the whole code =
generated in=20
current addressing space you can use such block of directives: </P><PRE =
class=3Dsmallcode>    repeat $-$$
        load a byte from $$+%-1
        store byte a xor c at $$+%-1
    end repeat
</PRE>
<P class=3Dsmalltext>and each byte of code will be xored with the value =
defined by=20
<SPAN class=3Dsmallcode>c</SPAN> constant. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>virtual</SPAN> defines =
virtual data at=20
specified address. This data will not be included in the output file, =
but labels=20
defined there can be used in other parts of source. This directive can =
be=20
followed by <SPAN class=3Dsmallcode>at</SPAN> operator and the numerical =

expression specifying the address for virtual data, otherwise is uses =
current=20
address, the same as <SPAN =
class=3Dsmallcode>virtual&nbsp;at&nbsp;$</SPAN>.=20
Instructions defining data are expected in next lines, ended with <SPAN=20
class=3Dsmallcode>end&nbsp;virtual</SPAN> directive. The block of =
virtual=20
instructions itself is an independent addressing space, after it's =
ended, the=20
context of previous addressing space is restored. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>virtual</SPAN> =
directive can be=20
used to create union of some variables, for example: </P><PRE =
class=3Dsmallcode>    GDTR dp ?
    virtual at GDTR
        GDT_limit dw ?
        GDT_address dd ?
    end virtual
</PRE>
<P class=3Dsmalltext>It defines two labels for parts of the 48-bit =
variable at=20
<SPAN class=3Dsmallcode>GDTR</SPAN> address. </P>
<P class=3Dsmalltext>It can be also used to define labels for some =
structures=20
addressed by a register, for example: </P><PRE class=3Dsmallcode>    =
virtual at bx
        LDT_limit dw ?
        LDT_address dd ?
    end virtual
</PRE>
<P class=3Dsmalltext>With such definition instruction <SPAN=20
class=3Dsmallcode>mov&nbsp;ax,[LDT_limit]</SPAN> will be assembled to =
the same=20
instruction as <SPAN class=3Dsmallcode>mov&nbsp;ax,[bx]</SPAN>. </P>
<P class=3Dsmalltext>Declaring defined data values or instructions =
inside the=20
virtual block would also be useful, because the <SPAN=20
class=3Dsmallcode>load</SPAN> directive can be used to load the values =
from the=20
virtually generated code into a constants. This directive should be used =
after=20
the code it loads but before the virtual block ends, because it can only =
load=20
the values from the same addressing space. For example: </P><PRE =
class=3Dsmallcode>    virtual at 0
        xor eax,eax
        and edx,eax
        load zeroq dword from 0
    end virtual
</PRE>
<P class=3Dsmalltext>The above piece of code will define the <SPAN=20
class=3Dsmallcode>zeroq</SPAN> constant containing four bytes of the =
machine code=20
of the instructions defined inside the virtual block. This method can be =
also=20
used to load some binary value from external file. For example this =
code: </P><PRE class=3Dsmallcode>    virtual at 0
        file 'a.txt':10h,1
        load char from 0
    end virtual
</PRE>
<P class=3Dsmalltext>loads the single byte from offset 10h in file <SPAN =

class=3Dsmallcode>a.txt</SPAN> into the <SPAN =
class=3Dsmallcode>char</SPAN>=20
constant. </P>
<P class=3Dsmalltext>Any of the <SPAN class=3Dsmallcode>section</SPAN> =
directives=20
described in <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.4">2.4</A> =
also begins=20
a new addressing space. </P>
<P><B><A class=3Dsmalltext name=3D2.2.5>2.2.5 Other directives</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>align</SPAN> directive =
aligns code or=20
data to the specified boundary. It should be followed by a numerical =
expression=20
specifying the number of bytes, to the multiply of which the current =
address has=20
to be aligned. The boundary value has to be the power of two. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>align</SPAN> directive =
fills the=20
bytes that had to be skipped to perform the alignment with the <SPAN=20
class=3Dsmallcode>nop</SPAN> instructions and at the same time marks =
this area as=20
uninitialized data, so if it is placed among other uninitialized data =
that=20
wouldn't take space in the output file, the alignment bytes will act the =
same=20
way. If you need to fill the alignment area with some other values, you =
can=20
combine <SPAN class=3Dsmallcode>align</SPAN> with <SPAN=20
class=3Dsmallcode>virtual</SPAN> to get the size of alignment needed and =
then=20
create the alignment yourself, like: </P><PRE class=3Dsmallcode>    =
virtual
        align 16
        a =3D $ - $$
    end virtual
    db a dup 0
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>a</SPAN> constant is =
defined to be=20
the difference between address after alignment and address of the <SPAN=20
class=3Dsmallcode>virtual</SPAN> block (see previous section), so it is =
equal to=20
the size of needed alignment space. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>display</SPAN> directive =
displays the=20
message at the assembly time. It should be followed by the quoted =
strings or=20
byte values, separated with commas. It can be used to display values of =
some=20
constants, for example: </P><PRE class=3Dsmallcode>    bits =3D 16
    display 'Current offset is 0x'
    repeat bits/4
        d =3D '0' + $ shr (bits-%*4) and 0Fh
        if d &gt; '9'
            d =3D d + 'A'-'9'-1
        end if
        display d
    end repeat
    display 13,10
</PRE>
<P class=3Dsmalltext>This block of directives calculates the four =
hexadecimal=20
digits of 16-bit value and converts them into characters for displaying. =
Note=20
that this will not work if the adresses in current addressing space are=20
relocatable (as it might happen with PE or object output formats), since =
only=20
absolute values can be used this way. The absolute value may be obtained =
by=20
calculating the relative address, like <SPAN =
class=3Dsmallcode>$-$$</SPAN>, or=20
<SPAN class=3Dsmallcode>rva&nbsp;$</SPAN> in case of PE format. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>err</SPAN> directive =
immediately=20
terminates the assembly process when it is encountered by assembler. =
</P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>assert</SPAN> directive =
tests=20
whether the logical expression that follows it is true, and if not, it=20
signalizes the error. </P>
<P><B><A class=3Dsmalltext name=3D2.2.6>2.2.6 Multiple passes</A> =
</B></P>
<P class=3Dsmalltext>Because the assembler allows to reference some of =
the labels=20
or constants before they get actually defined, it has to predict the =
values of=20
such labels and if there is even a suspicion that prediction failed in =
at least=20
one case, it does one more pass, assembling the whole source, this time =
doing=20
better prediction based on the values the labels got in the previous =
pass. </P>
<P class=3Dsmalltext>The changing values of labels can cause some =
instructions to=20
have encodings of different length, and this can cause the change in =
values of=20
labels again. And since the labels and constants can also be used inside =
the=20
expressions that affect the behavior of control directives, the whole =
block of=20
source can be processed completely differently during the new pass. Thus =
the=20
assembler does more and more passes, each time trying to do better =
predictions=20
to approach the final solution, when all the values get predicted =
correctly. It=20
uses various method for predicting the values, which has been chosen to =
allow=20
finding in a few passes the solution of possibly smallest length for the =
most of=20
the programs. </P>
<P class=3Dsmalltext>Some of the errors, like the values not fitting in =
required=20
boundaries, are not signaled during those intermediate passes, since it =
may=20
happen that when some of the values are predicted better, these errors =
will=20
disappear. However if assembler meets some illegal syntax construction =
or=20
unknown instruction, it always stops immediately. Also defining some =
label more=20
than once causes such error, because it makes the predictions =
groundless. </P>
<P class=3Dsmalltext>Only the messages created with the <SPAN=20
class=3Dsmallcode>display</SPAN> directive during the last performed =
pass get=20
actually displayed. In case when the assembly has been stopped due to an =
error,=20
these messages may reflect the predicted values that are not yet =
resolved=20
correctly. </P>
<P class=3Dsmalltext>The solution may sometimes not exist and in such =
cases the=20
assembler will never manage to make correct predictions - for this =
reason there=20
is a limit for a number of passes, and when assembler reaches this =
limit, it=20
stops and displays the message that it is not able to generate the =
correct=20
output. Consider the following example: </P><PRE class=3Dsmallcode>    =
if ~ defined alpha
        alpha:
    end if
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>defined</SPAN> operator =
gives the=20
true value when the expression following it could be calculated in this =
place,=20
what in this case means that the <SPAN class=3Dsmallcode>alpha</SPAN> =
label is=20
defined somewhere. But the above block causes this label to be defined =
only when=20
the value given by <SPAN class=3Dsmallcode>defined</SPAN> operator is =
false, what=20
leads to an antynomy and makes it impossible to resolve such code. When=20
processing the <SPAN class=3Dsmallcode>if</SPAN> directive assembler has =
to=20
predict whether the <SPAN class=3Dsmallcode>alpha</SPAN> label will be =
defined=20
somewhere (it wouldn't have to predict only if the label was already =
defined=20
earlier in this pass), and whatever the prediction is, the opposite =
always=20
happens. Thus the assembly will fail, unless the <SPAN=20
class=3Dsmallcode>alpha</SPAN> label is defined somewhere in source =
preceding the=20
above block of instructions - in such case, as it was already noted, the =

prediction is not needed and the block will just get skipped. </P>
<P class=3Dsmalltext>The above sample might have been written as a try =
to define=20
the label only when it was not yet defined. It fails, because the <SPAN=20
class=3Dsmallcode>defined</SPAN> operator does check whether the label =
is defined=20
anywhere, and this includes the definition inside this conditionally =
processed=20
block. However adding some additional condition may make it possible to =
get it=20
resolved: </P><PRE class=3Dsmallcode>    if ~ defined alpha | defined @f
        alpha:
        @@:
    end if
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>@f</SPAN> is always the =
same label=20
as the nearest <SPAN class=3Dsmallcode>@@</SPAN> symbol in the source =
following=20
it, so the above sample would mean the same if any unique name was used =
instead=20
of the anonymous label. When <SPAN class=3Dsmallcode>alpha</SPAN> is not =
defined=20
in any other place in source, the only possible solution is when this =
block gets=20
defined, and this time this doesn't lead to the antynomy, because of the =

anonymous label which makes this block self-establishing. To better =
understand=20
this, look at the blocks that has nothing more than this =
self-establishing: </P><PRE class=3Dsmallcode>    if defined @f
        @@:
    end if
</PRE>
<P class=3Dsmalltext>This is an example of source that may have more =
than one=20
solution, as both cases when this block gets processed or not are =
equally=20
correct. Which one of those two solutions we get depends on the =
algorithm on the=20
assembler, in case of flat assembler - on the algorithm of predictions. =
Back to=20
the previous sample, when <SPAN class=3Dsmallcode>alpha</SPAN> is not =
defined=20
anywhere else, the condition for <SPAN class=3Dsmallcode>if</SPAN> block =
cannot be=20
false, so we are left with only one possible solution, and we can hope =
the=20
assembler will arrive at it. On the other hand, when <SPAN=20
class=3Dsmallcode>alpha</SPAN> is defined in some other place, we've got =
two=20
possible solutions again, but one of them causes <SPAN=20
class=3Dsmallcode>alpha</SPAN> to be defined twice, and such an error =
causes=20
assembler to abort the assembly immediately, as this is the kind of =
error that=20
deeply disturbs the process of resolving. So we can get such source =
either=20
correctly resolved or causing an error, and what we get may depend on =
the=20
internal choices made by the assembler. </P>
<P class=3Dsmalltext>However there are some facts about such choices =
that are=20
certain. When assembler has to check whether the given symbol is defined =
and it=20
was already defined in the current pass, no prediction is needed - it =
was=20
already noted above. And when the given symbol has been defined never =
before,=20
including all the already finished passes, the assembler predicts it to =
be not=20
defined. Knowing this, we can expect that the simple self-establishing =
block=20
shown above will not be assembled at all and that the previous sample =
will=20
resolve correctly when <SPAN class=3Dsmallcode>alpha</SPAN> is defined =
somewhere=20
before our conditional block, while it will itself define <SPAN=20
class=3Dsmallcode>alpha</SPAN> when it's not already defined earlier, =
thus=20
potentially causing the error because of double definition if the <SPAN=20
class=3Dsmallcode>alpha</SPAN> is also defined somewhere later. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>used</SPAN> operator =
may be=20
expected to behave in a similar manner in analogous cases, however any =
other=20
kinds of predictions may not be so simple and you should never rely on =
them this=20
way. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>err</SPAN> directive, =
usually used=20
to stop the assembly when some condition is met, stops the assembly =
immediately,=20
regardless of whether the current pass is final or intermediate. So even =
when=20
the condition that caused this directive to be interpreted is temporary, =
and=20
would eventually disappear in the later passes, the assembly is stopped =
anyway.=20
</P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>assert</SPAN> directive =
signalizes=20
the error only if its expression is false after all the symbols have =
been=20
resolved. You can use <SPAN class=3Dsmallcode>assert&nbsp;0</SPAN> in =
place of=20
<SPAN class=3Dsmallcode>err</SPAN> when you do not want to have assembly =
stopped=20
during the intermediate passes. </P>
<P><B><A class=3Dmediumtext name=3D2.3>2.3 Preprocessor directives</A> =
</B></P>
<P class=3Dsmalltext>All preprocessor directives are processed before =
the main=20
assembly process, and therefore are not affected by the control =
directives. At=20
this time also all comments are stripped out. </P>
<P><B><A class=3Dsmalltext name=3D2.3.1>2.3.1 Including source files</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>include</SPAN> directive =
includes the=20
specified source file at the position where it is used. It should be =
followed by=20
the quoted name of file that should be included, for example: </P><PRE =
class=3Dsmallcode>    include 'macros.inc'
</PRE>
<P class=3Dsmalltext>The whole included file is preprocessed before =
preprocessing=20
the lines next to the line containing the <SPAN =
class=3Dsmallcode>include</SPAN>=20
directive. There are no limits to the number of included files as long =
as they=20
fit in memory. </P>
<P class=3Dsmalltext>The quoted path can contain environment variables =
enclosed=20
within <SPAN class=3Dsmallcode>%</SPAN> characters, they will be =
replaced with=20
their values inside the path, both the <SPAN class=3Dsmallcode>\</SPAN> =
and <SPAN=20
class=3Dsmallcode>/</SPAN> characters are allowed as a path separators. =
The file=20
is first searched for in the directory containing file which included it =
and=20
when it is not found there, the search is continued in the directories =
specified=20
in the environment variable called INCLUDE (the multiple paths separated =
with=20
semicolons can be defined there, they will be searched in the same order =
as=20
specified). If file was not found in any of these places, preprocessor =
looks for=20
it in the directory containing the main source file (the one specified =
in=20
command line). These rules concern also paths given with the <SPAN=20
class=3Dsmallcode>file</SPAN> directive. </P>
<P><B><A class=3Dsmalltext name=3D2.3.2>2.3.2 Symbolic constants</A> =
</B></P>
<P class=3Dsmalltext>The symbolic constants are different from the =
numerical=20
constants, before the assembly process they are replaced with their =
values=20
everywhere in source lines after their definitions, and anything can =
become=20
their values. </P>
<P class=3Dsmalltext>The definition of symbolic constant consists of =
name of the=20
constant followed by the <SPAN class=3Dsmallcode>equ</SPAN> directive. =
Everything=20
that follows this directive will become the value of constant. If the =
value of=20
symbolic constant contains other symbolic constants, they are replaced =
with=20
their values before assigning this value to the new constant. For =
example: </P><PRE class=3Dsmallcode>    d equ dword
    NULL equ d 0
    d equ edx
</PRE>
<P class=3Dsmalltext>After these three definitions the value of <SPAN=20
class=3Dsmallcode>NULL</SPAN> constant is <SPAN class=3Dsmallcode>dword =
0</SPAN> and=20
the value of <SPAN class=3Dsmallcode>d</SPAN> is <SPAN =
class=3Dsmallcode>edx</SPAN>.=20
So, for example, <SPAN class=3Dsmallcode>push NULL</SPAN> will be =
assembled as=20
<SPAN class=3Dsmallcode>push dword 0</SPAN> and <SPAN =
class=3Dsmallcode>push=20
d</SPAN> will be assembled as <SPAN class=3Dsmallcode>push edx</SPAN>. =
And if then=20
the following line was put: </P><PRE class=3Dsmallcode>    d equ d,eax
</PRE>
<P class=3Dsmalltext>the <SPAN class=3Dsmallcode>d</SPAN> constant would =
get the new=20
value of <SPAN class=3Dsmallcode>edx,eax</SPAN>. This way the growing =
lists of=20
symbols can be defined. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>restore</SPAN> directive =
allows to get=20
back previous value of redefined symbolic constant. It should be =
followed by one=20
more names of symbolic constants, separated with commas. So <SPAN=20
class=3Dsmallcode>restore d</SPAN> after the above definitions will give =
<SPAN=20
class=3Dsmallcode>d</SPAN> constant back the value <SPAN=20
class=3Dsmallcode>edx</SPAN>, the second one will restore it to value =
<SPAN=20
class=3Dsmallcode>dword</SPAN>, and one more will revert <SPAN=20
class=3Dsmallcode>d</SPAN> to original meaning as if no such constant =
was defined.=20
If there was no constant defined of given name, <SPAN=20
class=3Dsmallcode>restore</SPAN> will not cause an error, it will be =
just ignored.=20
</P>
<P class=3Dsmalltext>Symbolic constant can be used to adjust the syntax =
of=20
assembler to personal preferences. For example the following set of =
definitions=20
provides the handy shortcuts for all the size operators: </P><PRE =
class=3Dsmallcode>    b equ byte
    w equ word
    d equ dword
    p equ pword
    f equ fword
    q equ qword
    t equ tword
    x equ dqword
    y equ qqword
</PRE>
<P class=3Dsmalltext>Because symbolic constant may also have an empty =
value, it=20
can be used to allow the syntax with <SPAN =
class=3Dsmallcode>offset</SPAN> word=20
before any address value: </P><PRE class=3Dsmallcode>    offset equ
</PRE>
<P class=3Dsmalltext>After this definition <SPAN class=3Dsmallcode>mov =
ax,offset=20
char</SPAN> will be valid construction for copying the offset of <SPAN=20
class=3Dsmallcode>char</SPAN> variable into <SPAN =
class=3Dsmallcode>ax</SPAN>=20
register, because <SPAN class=3Dsmallcode>offset</SPAN> is replaced with =
an empty=20
value, and therefore ignored. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>define</SPAN> directive =
followed by=20
the name of constant and then the value, is the alternative way of =
defining=20
symbolic constant. The only difference between <SPAN=20
class=3Dsmallcode>define</SPAN> and <SPAN class=3Dsmallcode>equ</SPAN> =
is that <SPAN=20
class=3Dsmallcode>define</SPAN> assigns the value as it is, it does not =
replace=20
the symbolic constants with their values inside it. </P>
<P class=3Dsmalltext>Symbolic constants can also be defined with the =
<SPAN=20
class=3Dsmallcode>fix</SPAN> directive, which has the same syntax as =
<SPAN=20
class=3Dsmallcode>equ</SPAN>, but defines constants of high priority - =
they are=20
replaced with their symbolic values even before processing the =
preprocessor=20
directives and macroinstructions, the only exception is <SPAN=20
class=3Dsmallcode>fix</SPAN> directive itself, which has the highest =
possible=20
priority, so it allows redefinition of constants defined this way. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>fix</SPAN> directive =
can be used=20
for syntax adjustments related to directives of preprocessor, what =
cannot be=20
done with <SPAN class=3Dsmallcode>equ</SPAN> directive. For example: =
</P><PRE class=3Dsmallcode>    incl fix include
</PRE>
<P class=3Dsmalltext>defines a short name for <SPAN =
class=3Dsmallcode>include</SPAN>=20
directive, while the similar definition done with <SPAN=20
class=3Dsmallcode>equ</SPAN> directive wouldn't give such result, as =
standard=20
symbolic constants are replaced with their values after searching the =
line for=20
preprocessor directives. </P>
<P><B><A class=3Dsmalltext name=3D2.3.3>2.3.3 Macroinstructions</A> =
</B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>macro</SPAN> directive =
allows you to=20
define your own complex instructions, called macroinstructions, using =
which can=20
greatly simplify the process of programming. In its simplest form it's =
similar=20
to symbolic constant definition. For example the following definition =
defines a=20
shortcut for the <SPAN class=3Dsmallcode>test al,0xFF</SPAN> =
instruction: </P><PRE class=3Dsmallcode>    macro tst {test al,0xFF}
</PRE>
<P class=3Dsmalltext>After the <SPAN class=3Dsmallcode>macro</SPAN> =
directive there=20
is a name of macroinstruction and then its contents enclosed between the =
<SPAN=20
class=3Dsmallcode>{</SPAN> and <SPAN class=3Dsmallcode>}</SPAN> =
characters. You can=20
use <SPAN class=3Dsmallcode>tst</SPAN> instruction anywhere after this =
definition=20
and it will be assembled as <SPAN class=3Dsmallcode>test al,0xFF</SPAN>. =
Defining=20
symbolic constant <SPAN class=3Dsmallcode>tst</SPAN> of that value would =
give the=20
similar result, but the difference is that the name of macroinstruction =
is=20
recognized only as an instruction mnemonic. Also, macroinstructions are =
replaced=20
with corresponding code even before the symbolic constants are replaced =
with=20
their values. So if you define macroinstruction and symbolic constant of =
the=20
same name, and use this name as an instruction mnemonic, it will be =
replaced=20
with the contents of macroinstruction, but it will be replaced with =
value if=20
symbolic constant if used somewhere inside the operands. </P>
<P class=3Dsmalltext>The definition of macroinstruction can consist of =
many lines,=20
because <SPAN class=3Dsmallcode>{</SPAN> and <SPAN =
class=3Dsmallcode>}</SPAN>=20
characters don't have to be in the same line as <SPAN=20
class=3Dsmallcode>macro</SPAN> directive. For example: </P><PRE =
class=3Dsmallcode>    macro stos0
     {
        xor al,al
        stosb
     }
</PRE>
<P class=3Dsmalltext>The macroinstruction <SPAN =
class=3Dsmallcode>stos0</SPAN> will=20
be replaced with these two assembly instructions anywhere it's used. =
</P>
<P class=3Dsmalltext>Like instructions which needs some number of =
operands, the=20
macroinstruction can be defined to need some number of arguments =
separated with=20
commas. The names of needed argument should follow the name of =
macroinstruction=20
in the line of <SPAN class=3Dsmallcode>macro</SPAN> directive and should =
be=20
separated with commas if there is more than one. Anywhere one of these =
names=20
occurs in the contents of macroinstruction, it will be replaced with=20
corresponding value, provided when the macroinstruction is used. Here is =
an=20
example of a macroinstruction that will do data alignment for binary =
output=20
format: </P><PRE class=3Dsmallcode>    macro align value { rb =
(value-1)-($+value-1) mod value }
</PRE>
<P class=3Dsmalltext>When the <SPAN class=3Dsmallcode>align 4</SPAN> =
instruction is=20
found after this macroinstruction is defined, it will be replaced with =
contents=20
of this macroinstruction, and the <SPAN class=3Dsmallcode>value</SPAN> =
will there=20
become 4, so the result will be <SPAN class=3Dsmallcode>rb (4-1)-($+4-1) =
mod=20
4</SPAN>. </P>
<P class=3Dsmalltext>If a macroinstruction is defined that uses an =
instruction=20
with the same name inside its definition, the previous meaning of this =
name is=20
used. Useful redefinition of macroinstructions can be done in that way, =
for=20
example: </P><PRE class=3Dsmallcode>    macro mov op1,op2
     {
      if op1 in &lt;ds,es,fs,gs,ss&gt; &amp; op2 in =
&lt;cs,ds,es,fs,gs,ss&gt;
        push  op2
        pop   op1
      else
        mov   op1,op2
      end if
     }
</PRE>
<P class=3Dsmalltext>This macroinstruction extends the syntax of <SPAN=20
class=3Dsmallcode>mov</SPAN> instruction, allowing both operands to be =
segment=20
registers. For example <SPAN class=3Dsmallcode>mov ds,es</SPAN> will be =
assembled=20
as <SPAN class=3Dsmallcode>push es</SPAN> and <SPAN =
class=3Dsmallcode>pop ds</SPAN>.=20
In all other cases the standard <SPAN class=3Dsmallcode>mov</SPAN> =
instruction=20
will be used. The syntax of this <SPAN class=3Dsmallcode>mov</SPAN> can =
be=20
extended further by defining next macroinstruction of that name, which =
will use=20
the previous macroinstruction: </P><PRE class=3Dsmallcode>    macro mov =
op1,op2,op3
     {
      if op3 eq
        mov   op1,op2
      else
        mov   op1,op2
        mov   op2,op3
      end if
     }
</PRE>
<P class=3Dsmalltext>It allows <SPAN class=3Dsmallcode>mov</SPAN> =
instruction to=20
have three operands, but it can still have two operands only, because =
when=20
macroinstruction is given less arguments than it needs, the rest of =
arguments=20
will have empty values. When three operands are given, this =
macroinstruction=20
will become two macroinstructions of the previous definition, so <SPAN=20
class=3Dsmallcode>mov es,ds,dx</SPAN> will be assembled as <SPAN=20
class=3Dsmallcode>push ds</SPAN>, <SPAN class=3Dsmallcode>pop es</SPAN> =
and <SPAN=20
class=3Dsmallcode>mov ds,dx</SPAN>. </P>
<P class=3Dsmalltext>By placing the <SPAN class=3Dsmallcode>*</SPAN> =
after the name=20
of argument you can mark the argument as required - preprocessor will =
not allow=20
it to have an empty value. For example the above macroinstruction could =
be=20
declared as <SPAN =
class=3Dsmallcode>macro&nbsp;mov&nbsp;op1*,op2*,op3</SPAN> to=20
make sure that first two arguments will always have to be given some non =
empty=20
values. </P>
<P class=3Dsmalltext>Alternatively, you can provide the default value =
for=20
argument, by placing the <SPAN class=3Dsmallcode>=3D</SPAN> followed by =
value after=20
the name of argument. Then if the argument has an empty value provided, =
the=20
default value will be used instead. </P>
<P class=3Dsmalltext>When it's needed to provide macroinstruction with =
argument=20
that contains some commas, such argument should be enclosed between =
<SPAN=20
class=3Dsmallcode>&lt;</SPAN> and <SPAN class=3Dsmallcode>&gt;</SPAN> =
characters. If=20
it contains more than one <SPAN class=3Dsmallcode>&lt;</SPAN> character, =
the same=20
number of <SPAN class=3Dsmallcode>&gt;</SPAN> should be used to tell =
that the=20
value of argument ends. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>purge</SPAN> directive =
allows removing=20
the last definition of specified macroinstruction. It should be followed =
by one=20
or more names of macroinstructions, separated with commas. If such=20
macroinstruction has not been defined, you will not get any error. For =
example=20
after having the syntax of <SPAN class=3Dsmallcode>mov</SPAN> extended =
with the=20
macroinstructions defined above, you can disable syntax with three =
operands back=20
by using <SPAN class=3Dsmallcode>purge mov</SPAN> directive. Next <SPAN=20
class=3Dsmallcode>purge mov</SPAN> will disable also syntax for two =
operands being=20
segment registers, and all the next such directives will do nothing. =
</P>
<P class=3Dsmalltext>If after the <SPAN class=3Dsmallcode>macro</SPAN> =
directive you=20
enclose some group of arguments' names in square brackets, it will allow =
giving=20
more values for this group of arguments when using that =
macroinstruction. Any=20
more argument given after the last argument of such group will begin the =
new=20
group and will become the first argument of it. That's why after closing =
the=20
square bracket no more argument names can follow. The contents of=20
macroinstruction will be processed for each such group of arguments =
separately.=20
The simplest example is to enclose one argument name in square brackets: =
</P><PRE class=3Dsmallcode>    macro stoschar [char]
     {
        mov al,char
        stosb
     }
</PRE>
<P class=3Dsmalltext>This macroinstruction accepts unlimited number of =
arguments,=20
and each one will be processed into these two instructions separately. =
For=20
example <SPAN class=3Dsmallcode>stoschar 1,2,3</SPAN> will be assembled =
as the=20
following instructions: </P><PRE class=3Dsmallcode>    mov al,1
    stosb
    mov al,2
    stosb
    mov al,3
    stosb
</PRE>
<P class=3Dsmalltext>There are some special directives available only =
inside the=20
definitions of macroinstructions. <SPAN class=3Dsmallcode>local</SPAN> =
directive=20
defines local names, which will be replaced with unique values each time =
the=20
macroinstruction is used. It should be followed by names separated with =
commas.=20
If the name given as parameter to <SPAN class=3Dsmallcode>local</SPAN> =
directive=20
begins with a dot or two dots, the unique labels generated by each =
evaluation of=20
macroinstruction will have the same properties. This directive is =
usually needed=20
for the constants or labels that macroinstruction defines and uses =
internally.=20
For example: </P><PRE class=3Dsmallcode>    macro movstr
     {
        local move
      move:
        lodsb
        stosb
        test al,al
        jnz move
     }
</PRE>
<P class=3Dsmalltext>Each time this macroinstruction is used, <SPAN=20
class=3Dsmallcode>move</SPAN> will become other unique name in its =
instructions,=20
so you will not get an error you normally get when some label is defined =
more=20
than once. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>forward</SPAN>, <SPAN=20
class=3Dsmallcode>reverse</SPAN> and <SPAN =
class=3Dsmallcode>common</SPAN>=20
directives divide macroinstruction into blocks, each one processed after =
the=20
processing of previous is finished. They differ in behavior only if=20
macroinstruction allows multiple groups of arguments. Block of =
instructions that=20
follows <SPAN class=3Dsmallcode>forward</SPAN> directive is processed =
for each=20
group of arguments, from first to last - exactly like the default block =
(not=20
preceded by any of these directives). Block that follows <SPAN=20
class=3Dsmallcode>reverse</SPAN> directive is processed for each group =
of argument=20
in reverse order - from last to first. Block that follows <SPAN=20
class=3Dsmallcode>common</SPAN> directive is processed only once, =
commonly for all=20
groups of arguments. Local name defined in one of the blocks is =
available in all=20
the following blocks when processing the same group of arguments as when =
it was=20
defined, and when it is defined in common block it is available in all =
the=20
following blocks not depending on which group of arguments is processed. =
</P>
<P class=3Dsmalltext>Here is an example of macroinstruction that will =
create the=20
table of addresses to strings followed by these strings: </P><PRE =
class=3Dsmallcode>    macro strtbl name,[string]
     {
      common
        label name dword
      forward
        local label
        dd label
      forward
        label db string,0
     }
</PRE>
<P class=3Dsmalltext>First argument given to this macroinstruction will =
become the=20
label for table of addresses, next arguments should be the strings. =
First block=20
is processed only once and defines the label, second block for each =
string=20
declares its local name and defines the table entry holding the address =
to that=20
string. Third block defines the data of each string with the =
corresponding=20
label. </P>
<P class=3Dsmalltext>The directive starting the block in =
macroinstruction can be=20
followed by the first instruction of this block in the same line, like =
in the=20
following example: </P><PRE class=3Dsmallcode>    macro stdcall =
proc,[arg]
     {
      reverse push arg
      common call proc
     }
</PRE>
<P class=3Dsmalltext>This macroinstruction can be used for calling the =
procedures=20
using STDCALL convention, which has all the arguments pushed on stack in =
the=20
reverse order. For example <SPAN class=3Dsmallcode>stdcall =
foo,1,2,3</SPAN> will=20
be assembled as: </P><PRE class=3Dsmallcode>    push 3
    push 2
    push 1
    call foo
</PRE>
<P class=3Dsmalltext>If some name inside macroinstruction has multiple =
values (it=20
is either one of the arguments enclosed in square brackets or local name =
defined=20
in the block following <SPAN class=3Dsmallcode>forward</SPAN> or <SPAN=20
class=3Dsmallcode>reverse</SPAN> directive) and is used in block =
following the=20
<SPAN class=3Dsmallcode>common</SPAN> directive, it will be replaced =
with all of=20
its values, separated with commas. For example the following =
macroinstruction=20
will pass all of the additional arguments to the previously defined =
<SPAN=20
class=3Dsmallcode>stdcall</SPAN> macroinstruction: </P><PRE =
class=3Dsmallcode>    macro invoke proc,[arg]
     { common stdcall [proc],arg }
</PRE>
<P class=3Dsmalltext>It can be used to call indirectly (by the pointer =
stored in=20
memory) the procedure using STDCALL convention. </P>
<P class=3Dsmalltext>Inside macroinstruction also special operator <SPAN =

class=3Dsmallcode>#</SPAN> can be used. This operator causes two names =
to be=20
concatenated into one name. It can be useful, because it's done after =
the=20
arguments and local names are replaced with their values. The following=20
macroinstruction will generate the conditional jump according to the =
<SPAN=20
class=3Dsmallcode>cond</SPAN> argument: </P><PRE class=3Dsmallcode>    =
macro jif op1,cond,op2,label
     {
        cmp op1,op2
        j#cond label
     }
</PRE>
<P class=3Dsmalltext>For example <SPAN class=3Dsmallcode>jif =
ax,ae,10h,exit</SPAN>=20
will be assembled as <SPAN class=3Dsmallcode>cmp ax,10h</SPAN> and <SPAN =

class=3Dsmallcode>jae exit</SPAN> instructions. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>#</SPAN> operator can =
be also used=20
to concatenate two quoted strings into one. Also conversion of name into =
a=20
quoted string is possible, with the <SPAN class=3Dsmallcode>`</SPAN> =
operator,=20
which likewise can be used inside the macroinstruction. It converts the =
name=20
that follows it into a quoted string - but note, that when it is =
followed by a=20
macro argument which is being replaced with value containing more than =
one=20
symbol, only the first of them will be converted, as the <SPAN=20
class=3Dsmallcode>`</SPAN> operator converts only one symbol that =
immediately=20
follows it. Here's an example of utilizing those two features: </P><PRE =
class=3Dsmallcode>    macro label name
     {
        label name
        if ~ used name
          display `name # " is defined but not used.",13,10
        end if
     }
</PRE>
<P class=3Dsmalltext>When label defined with such macro is not used in =
the source,=20
macro will warn you with the message, informing to which label it =
applies. </P>
<P class=3Dsmalltext>To make macroinstruction behaving differently when =
some of=20
the arguments are of some special type, for example a quoted strings, =
you can=20
use <SPAN class=3Dsmallcode>eqtype</SPAN> comparision operator. Here's =
an example=20
of utilizing it to distinguish a quoted string from an other argument: =
</P><PRE class=3Dsmallcode>    macro message arg
     {
      if arg eqtype ""
        local str
        jmp   @f
        str   db arg,0Dh,0Ah,24h
        @@:
        mov   dx,str
      else
        mov   dx,arg
      end if
        mov   ah,9
        int   21h
     }
</PRE>
<P class=3Dsmalltext>The above macro is designed for displaying messages =
in DOS=20
programs. When the argument of this macro is some number, label, or =
variable,=20
the string from that address is displayed, but when the argument is a =
quoted=20
string, the created code will display that string followed by the =
carriage=20
return and line feed. </P>
<P class=3Dsmalltext>It is also possible to put a declaration of =
macroinstruction=20
inside another macroinstruction, so one macro can define another, but =
there is a=20
problem with such definitions caused by the fact, that <SPAN=20
class=3Dsmallcode>}</SPAN> character cannot occur inside the =
macroinstruction, as=20
it always means the end of definition. To overcome this problem, the =
escaping of=20
symbols inside macroinstruction can be used. This is done by placing one =
or more=20
backslashes in front of any other symbol (even the special character).=20
Preprocessor sees such sequence as a single symbol, but each time it =
meets such=20
symbol during the macroinstruction processing, it cuts the backslash =
character=20
from the front of it. For example <SPAN class=3Dsmallcode>\}</SPAN> is =
treated as=20
single symbol, but during processing of the macroinstruction it becomes =
the=20
<SPAN class=3Dsmallcode>}</SPAN> symbol. This allows to put one =
definition of=20
macroinstruction inside another: </P><PRE class=3Dsmallcode>    macro =
ext instr
     {
      macro instr op1,op2,op3
       \{
        if op3 eq
          instr op1,op2
        else
          instr op1,op2
          instr op2,op3
        end if
       \}
     }

    ext add
    ext sub
</PRE>
<P class=3Dsmalltext>The macro <SPAN class=3Dsmallcode>ext</SPAN> is =
defined=20
correctly, but when it is used, the <SPAN class=3Dsmallcode>\{</SPAN> =
and <SPAN=20
class=3Dsmallcode>\}</SPAN> become the <SPAN class=3Dsmallcode>{</SPAN> =
and <SPAN=20
class=3Dsmallcode>}</SPAN> symbols. So when the <SPAN=20
class=3Dsmallcode>ext&nbsp;add</SPAN> is processed, the contents of =
macro becomes=20
valid definition of a macroinstruction and this way the<SPAN=20
class=3Dsmallcode>add</SPAN> macro becomes defined. In the same way<SPAN =

class=3Dsmallcode>ext&nbsp;sub</SPAN> defines the<SPAN =
class=3Dsmallcode>sub</SPAN>=20
macro. The use of <SPAN class=3Dsmallcode>\{</SPAN> symbol wasn't really =
necessary=20
here, but it's done this way to make the definition more clear. </P>
<P class=3Dsmalltext>If some directives specific to macroinstructions, =
like <SPAN=20
class=3Dsmallcode>local</SPAN> or <SPAN class=3Dsmallcode>common</SPAN> =
are needed=20
inside some macro embedded this way, they can be escaped in the same =
way.=20
Escaping the symbol with more than one backslash is also allowed, which =
allows=20
multiple levels of nesting the macroinstruction definitions. </P>
<P class=3Dsmalltext>The another technique for defining one =
macroinstruction by=20
another is to use the <SPAN class=3Dsmallcode>fix</SPAN> directive, =
which becomes=20
useful when some macroinstruction only begins the definition of another =
one,=20
without closing it. For example: </P><PRE class=3Dsmallcode>    macro =
tmacro [params]
     {
      common macro params {
     }

    MACRO fix tmacro
    ENDM fix }
</PRE>
<P class=3Dsmalltext>defines an alternative syntax for defining =
macroinstructions,=20
which looks like: </P><PRE class=3Dsmallcode>    MACRO stoschar char
        mov al,char
        stosb
    ENDM
</PRE>
<P class=3Dsmalltext>Note that symbol that has such customized =
definition must be=20
defined with <SPAN class=3Dsmallcode>fix</SPAN> directive, because only =
the=20
prioritized symbolic constants are processed before the preprocessor =
looks for=20
the <SPAN class=3Dsmallcode>}</SPAN> character while defining the macro. =
This=20
might be a problem if one needed to perform some additional tasks one =
the end of=20
such definition, but there is one more feature which helps in such =
cases. Namely=20
it is possible to put any directive, instruction or macroinstruction =
just after=20
the <SPAN class=3Dsmallcode>}</SPAN> character that ends the =
macroinstruction and=20
it will be processed in the same way as if it was put in the next line. =
</P>
<P><B><A class=3Dsmalltext name=3D2.3.4>2.3.4 Structures</A> </B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>struc</SPAN> directive is a =
special=20
variant of <SPAN class=3Dsmallcode>macro</SPAN> directive that is used =
to define=20
data structures. Macroinstruction defined using the <SPAN=20
class=3Dsmallcode>struc</SPAN> directive must be preceded by a label =
(like the=20
data definition directive) when it's used. This label will be also =
attached at=20
the beginning of every name starting with dot in the contents of=20
macroinstruction. The macroinstruction defined using the <SPAN=20
class=3Dsmallcode>struc</SPAN> directive can have the same name as some =
other=20
macroinstruction defined using the <SPAN class=3Dsmallcode>macro</SPAN> =
directive,=20
structure macroinstruction will not prevent the standard =
macroinstruction from=20
being processed when there is no label before it and vice versa. All the =
rules=20
and features concerning standard macroinstructions apply to structure=20
macroinstructions. </P>
<P class=3Dsmalltext>Here is the sample of structure macroinstruction: =
</P><PRE class=3Dsmallcode>    struc point x,y
     {
        .x dw x
        .y dw y
     }
</PRE>
<P class=3Dsmalltext>For example <SPAN class=3Dsmallcode>my point =
7,11</SPAN> will=20
define structure labeled <SPAN class=3Dsmallcode>my</SPAN>, consisting =
of two=20
variables: <SPAN class=3Dsmallcode>my.x</SPAN> with value 7 and <SPAN=20
class=3Dsmallcode>my.y</SPAN> with value 11. </P>
<P class=3Dsmalltext>If somewhere inside the definition of structure the =
name=20
consisting of a single dot it found, it is replaced by the name of the =
label for=20
the given instance of structure and this label will not be defined =
automatically=20
in such case, allowing to completely customize the definition. The =
following=20
example utilizes this feature to extend the data definition directive =
<SPAN=20
class=3Dsmallcode>db</SPAN> with ability to calculate the size of =
defined data:=20
</P><PRE class=3Dsmallcode>    struc db [data]
     {
       common
        . db data
        .size =3D $ - .
     }
</PRE>
<P class=3Dsmalltext>With such definition <SPAN class=3Dsmallcode>msg db =

'Hello!',13,10</SPAN> will define also <SPAN =
class=3Dsmallcode>msg.size</SPAN>=20
constant, equal to the size of defined data in bytes. </P>
<P class=3Dsmalltext>Defining data structures addressed by registers or =
absolute=20
values should be done using the <SPAN class=3Dsmallcode>virtual</SPAN> =
directive=20
with structure macroinstruction (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.4">2.2.4</=
A>). </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>restruc</SPAN> directive =
removes the=20
last definition of the structure, just like <SPAN =
class=3Dsmallcode>purge</SPAN>=20
does with macroinstructions and <SPAN class=3Dsmallcode>restore</SPAN> =
with=20
symbolic constants. It also has the same syntax - should be followed by =
one or=20
more names of structure macroinstructions, separated with commas. </P>
<P><B><A class=3Dsmalltext name=3D2.3.5>2.3.5 Repeating =
macroinstructions</A>=20
</B></P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>rept</SPAN> directive =
is a special=20
kind of macroinstruction, which makes given amount of duplicates of the =
block=20
enclosed with braces. The basic syntax is <SPAN =
class=3Dsmallcode>rept</SPAN>=20
directive followed by number. and then block of source enclosed between =
the=20
<SPAN class=3Dsmallcode>{</SPAN> and <SPAN class=3Dsmallcode>}</SPAN> =
characters.=20
The simplest example: </P><PRE class=3Dsmallcode>    rept 5 { in al,dx }
</PRE>
<P class=3Dsmalltext>will make five duplicates of the <SPAN =
class=3Dsmallcode>in=20
al,dx</SPAN> line. The block of instructions is defined in the same way =
as for=20
the standard macroinstruction and any special operators and directives =
which can=20
be used only inside macroinstructions are also allowed here. When the =
given=20
count is zero, the block is simply skipped, as if you defined =
macroinstruction=20
but never used it. The number of repetitions can be followed by the name =
of=20
counter symbol, which will get replaced symbolically with the number of=20
duplicate currently generated. So this: </P><PRE class=3Dsmallcode>    =
rept 3 counter
     {
        byte#counter db counter
     }
</PRE>
<P class=3Dsmalltext>will generate lines: </P><PRE class=3Dsmallcode>    =
byte1 db 1
    byte2 db 2
    byte3 db 3
</PRE>
<P class=3Dsmalltext>The repetition mechanism applied to <SPAN=20
class=3Dsmallcode>rept</SPAN> blocks is the same as the one used to =
process=20
multiple groups of arguments for macroinstructions, so directives like =
<SPAN=20
class=3Dsmallcode>forward</SPAN>, <SPAN class=3Dsmallcode>common</SPAN> =
and <SPAN=20
class=3Dsmallcode>reverse</SPAN> can be used in their usual meaning. =
Thus such=20
macroinstruction: </P><PRE class=3Dsmallcode>    rept 7 num { reverse =
display `num }
</PRE>
<P class=3Dsmalltext>will display digits from 7 to 1 as text. The <SPAN=20
class=3Dsmallcode>local</SPAN> directive behaves in the same way as =
inside=20
macroinstruction with multiple groups of arguments, so: </P><PRE =
class=3Dsmallcode>    rept 21
     {
       local label
       label: loop label
     }
</PRE>
<P class=3Dsmalltext>will generate unique label for each duplicate. </P>
<P class=3Dsmalltext>The counter symbol by default counts from 1, but =
you can=20
declare different base value by placing the number preceded by colon =
immediately=20
after the name of counter. For example: </P><PRE class=3Dsmallcode>    =
rept 8 n:0 { pxor xmm#n,xmm#n }
</PRE>
<P class=3Dsmalltext>will generate code which will clear the contents of =
eight SSE=20
registers. You can define multiple counters separated with commas, and =
each one=20
can have different base. </P>
<P class=3Dsmalltext>The number of repetitions and the base values for =
counters=20
can be specified using the numerical expressions with operator rules =
identical=20
as in the case of assembler. However each value used in such expression =
must=20
either be a directly specified number, or a symbolic constant with value =
also=20
being an expression that can be calculated by preprocessor (in such case =
the=20
value of expression associated with symbolic constant is calculated =
first, and=20
then substituted into the outer expression in place of that constant). =
If you=20
need repetitions based on values that can only be calculated at assembly =
time,=20
use one of the code repeating directives that are processed by =
assembler, see=20
section <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.2.3">2.2.3</=
A>. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>irp</SPAN> directive =
iterates the=20
single argument through the given list of parameters. The syntax is =
<SPAN=20
class=3Dsmallcode>irp</SPAN> followed by the argument name, then the =
comma and=20
then the list of parameters. The parameters are specified in the same =
way like=20
in the invocation of standard macroinstruction, so they have to be =
separated=20
with commas and each one can be enclosed with the <SPAN=20
class=3Dsmallcode>&lt;</SPAN> and <SPAN class=3Dsmallcode>&gt;</SPAN> =
characters.=20
Also the name of argument may be followed by <SPAN =
class=3Dsmallcode>*</SPAN> to=20
mark that it cannot get an empty value. Such block: </P><PRE =
class=3Dsmallcode>   irp value, 2,3,5
    { db value }
</PRE>
<P class=3Dsmalltext>will generate lines: </P><PRE class=3Dsmallcode>   =
db 2
   db 3
   db 5
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>irps</SPAN> directive =
iterates=20
through the given list of symbols, it should be followed by the argument =
name,=20
then the comma and then the sequence of any symbols. Each symbol in this =

sequence, no matter whether it is the name symbol, symbol character or =
quoted=20
string, becomes an argument value for one iteration. If there are no =
symbols=20
following the comma, no iteration is done at all. This example: </P><PRE =
class=3Dsmallcode>   irps reg, al bx ecx
    { xor reg,reg }
</PRE>
<P class=3Dsmalltext>will generate lines: </P><PRE class=3Dsmallcode>   =
xor al,al
   xor bx,bx
   xor ecx,ecx
</PRE>
<P class=3Dsmalltext>The blocks defined by the <SPAN =
class=3Dsmallcode>irp</SPAN>=20
and <SPAN class=3Dsmallcode>irps</SPAN> directives are also processed in =
the same=20
way as any macroinstructions, so operators and directives specific to=20
macroinstructions may be freely used also in this case. </P>
<P><B><A class=3Dsmalltext name=3D2.3.6>2.3.6 Conditional =
preprocessing</A> </B></P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>match</SPAN> directive =
causes some=20
block of source to be preprocessed and passed to assembler only when the =
given=20
sequence of symbols matches the specified pattern. The pattern comes =
first,=20
ended with comma, then the symbols that have to be matched with the =
pattern, and=20
finally the block of source, enclosed within braces as macroinstruction. =
There=20
are the few rules for building the expression for matching, first is =
that any of=20
symbol characters and any quoted string should be matched exactly as is. =
In this=20
example: </P><PRE class=3Dsmallcode>    match +,+ { include 'first.inc' =
}
    match +,- { include 'second.inc' }
</PRE>
<P class=3Dsmalltext>the first file will get included, since <SPAN=20
class=3Dsmallcode>+</SPAN> after comma matches the <SPAN =
class=3Dsmallcode>+</SPAN>=20
in pattern, and the second file will not be included, since there is no =
match.=20
</P>
<P class=3Dsmalltext>To match any other symbol literally, it has to be =
preceded by=20
<SPAN class=3Dsmallcode>=3D</SPAN> character in the pattern. Also to =
match the <SPAN=20
class=3Dsmallcode>=3D</SPAN> character itself, or the comma, the <SPAN=20
class=3Dsmallcode>=3D=3D</SPAN> and <SPAN class=3Dsmallcode>=3D,</SPAN> =
constructions have=20
to be used. For example the <SPAN class=3Dsmallcode>=3Da=3D=3D</SPAN> =
pattern will match=20
the <SPAN class=3Dsmallcode>a=3D</SPAN> sequence. </P>
<P class=3Dsmalltext>If some name symbol is placed in the pattern, it =
matches any=20
sequence consisting of at least one symbol and then this name is =
replaced with=20
the matched sequence everywhere inside the following block, analogously =
to the=20
parameters of macroinstruction. For instance: </P><PRE =
class=3Dsmallcode>    match a-b, 0-7
     { dw a,b-a }
</PRE>
<P class=3Dsmalltext>will generate the <SPAN class=3Dsmallcode>dw =
0,7-0</SPAN>=20
instruction. Each name is always matched with as few symbols as =
possible,=20
leaving the rest for the following ones, so in this case: </P><PRE =
class=3Dsmallcode>    match a b, 1+2+3 { db a }
</PRE>
<P class=3Dsmalltext>the <SPAN class=3Dsmallcode>a</SPAN> name will =
match the <SPAN=20
class=3Dsmallcode>1</SPAN> symbol, leaving the <SPAN =
class=3Dsmallcode>+2+3</SPAN>=20
sequence to be matched with <SPAN class=3Dsmallcode>b</SPAN>. But in =
this case:=20
</P><PRE class=3Dsmallcode>    match a b, 1 { db a }
</PRE>
<P class=3Dsmalltext>there will be nothing left for <SPAN =
class=3Dsmallcode>b</SPAN>=20
to match, so the block will not get processed at all. </P>
<P class=3Dsmalltext>The block of source defined by match is processed =
in the same=20
way as any macroinstruction, so any operators specific to =
macroinstructions can=20
be used also in this case. </P>
<P class=3Dsmalltext>What makes <SPAN class=3Dsmallcode>match</SPAN> =
directive more=20
useful is the fact, that it replaces the symbolic constants with their =
values in=20
the matched sequence of symbols (that is everywhere after comma up to =
the=20
beginning of the source block) before performing the match. Thanks to =
this it=20
can be used for example to process some block of source under the =
condition that=20
some symbolic constant has the given value, like: </P><PRE =
class=3Dsmallcode>    match =3DTRUE, DEBUG { include 'debug.inc' }
</PRE>
<P class=3Dsmalltext>which will include the file only when the symbolic =
constant=20
<SPAN class=3Dsmallcode>DEBUG</SPAN> was defined with value <SPAN=20
class=3Dsmallcode>TRUE</SPAN>. </P>
<P><B><A class=3Dsmalltext name=3D2.3.7>2.3.7 Order of processing</A> =
</B></P>
<P class=3Dsmalltext>When combining various features of the =
preprocessor, it's=20
important to know the order in which they are processed. As it was =
already=20
noted, the highest priority has the <SPAN class=3Dsmallcode>fix</SPAN> =
directive=20
and the replacements defined with it. This is done completely before =
doing any=20
other preprocessing, therefore this piece of source: </P><PRE =
class=3Dsmallcode>    V fix {
      macro empty
       V
    V fix }
       V
</PRE>
<P class=3Dsmalltext>becomes a valid definition of an empty =
macroinstruction. It=20
can be interpreted that the <SPAN class=3Dsmallcode>fix</SPAN> directive =
and=20
prioritized symbolic constants are processed in a separate stage, and =
all other=20
preprocessing is done after on the resulting source. </P>
<P class=3Dsmalltext>The standard preprocessing that comes after, on =
each line=20
begins with recognition of the first symbol. It starts with checking for =
the=20
preprocessor directives, and when none of them is detected, preprocessor =
checks=20
whether the first symbol is macroinstruction. If no macroinstruction is =
found,=20
it moves to the second symbol of line, and again begins with checking =
for=20
directives, which in this case is only the <SPAN =
class=3Dsmallcode>equ</SPAN>=20
directive, as this is the only one that occurs as the second symbol in =
line. If=20
there is no directive, the second symbol is checked for the case of =
structure=20
macroinstruction and when none of those checks gives the positive =
result, the=20
symbolic constants are replaced with their values and such line is =
passed to the=20
assembler. </P>
<P class=3Dsmalltext>To see it on the example, assume that there is =
defined the=20
macroinstruction called <SPAN class=3Dsmallcode>foo</SPAN> and the =
structure=20
macroinstruction called <SPAN class=3Dsmallcode>bar</SPAN>. Those lines: =
</P><PRE class=3Dsmallcode>    foo equ
    foo bar
</PRE>
<P class=3Dsmalltext>would be then both interpreted as invocations of=20
macroinstruction <SPAN class=3Dsmallcode>foo</SPAN>, since the meaning =
of the=20
first symbol overrides the meaning of second one. </P>
<P class=3Dsmalltext>When the macroinstruction generates the new lines =
from its=20
definition block, in every line it first scans for macroinstruction =
directives,=20
and interpretes them accordingly. All the other content in the =
definition block=20
is used to brew the new lines, replacing the parameters with their =
values and=20
then processing the symbol escaping and <SPAN class=3Dsmallcode>#</SPAN> =
and <SPAN=20
class=3Dsmallcode>`</SPAN> operators. The conversion operator has the =
higher=20
priority than concatenation and if any of them operates on the escaped =
symbol,=20
the escaping is cancelled before finishing the operation. After this is=20
completed, the newly generated line goes through the standard =
preprocessing, as=20
described above. </P>
<P class=3Dsmalltext>Though the symbolic constants are usually only =
replaced in=20
the lines, where no preprocessor directives nor macroinstructions has =
been=20
found, there are some special cases where those replacements are =
performed in=20
the parts of lines containing directives. First one is the definition of =

symbolic constant, where the replacements are done everywhere after the =
<SPAN=20
class=3Dsmallcode>equ</SPAN> keyword and the resulting value is then =
assigned to=20
the new constant (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.2">2.3.2</=
A>). The=20
second such case is the <SPAN class=3Dsmallcode>match</SPAN> directive, =
where the=20
replacements are done in the symbols following comma before matching =
them with=20
pattern. These features can be used for example to maintain the lists, =
like this=20
set of definitions: </P><PRE class=3Dsmallcode>    list equ

    macro append item
     {
       match any, list \{ list equ list,item \}
       match , list \{ list equ item \}
     }
</PRE>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>list</SPAN> constant is =
here=20
initialized with empty value, and the <SPAN =
class=3Dsmallcode>append</SPAN>=20
macroinstruction can be used to add the new items into this list, =
separating=20
them with commas. The first match in this macroinstruction occurs only =
when the=20
value of list is not empty (see <A=20
href=3D"http://flatassembler.net/docs.php?article=3Dmanual#2.3.6">2.3.6</=
A>), in=20
such case the new value for the list is the previous one with the comma =
and the=20
new item appended at the end. The second match happens only when the =
list is=20
still empty, and in such case the list is defined to contain just the =
new item.=20
So starting with the empty list, the <SPAN =
class=3Dsmallcode>append&nbsp;1</SPAN>=20
would define <SPAN class=3Dsmallcode>list&nbsp;equ&nbsp;1</SPAN> and the =
<SPAN=20
class=3Dsmallcode>append&nbsp;2</SPAN> following it would define <SPAN=20
class=3Dsmallcode>list&nbsp;equ&nbsp;1,2</SPAN>. One might then need to =
use this=20
list as the parameters to some macroinstruction. But it cannot be done =
directly=20
- if <SPAN class=3Dsmallcode>foo</SPAN> is the macroinstruction, then =
<SPAN=20
class=3Dsmallcode>foo&nbsp;list</SPAN> would just pass the <SPAN=20
class=3Dsmallcode>list</SPAN> symbol as a parameter to macro, since =
symbolic=20
constants are not unrolled at this stage. For this purpose again <SPAN=20
class=3Dsmallcode>match</SPAN> directive comes in handy: </P><PRE =
class=3Dsmallcode>    match params, list { foo params }
</PRE>
<P class=3Dsmalltext>The value of <SPAN class=3Dsmallcode>list</SPAN>, =
if it's not=20
empty, matches the <SPAN class=3Dsmallcode>params</SPAN> keyword, which =
is then=20
replaced with matched value when generating the new lines defined by the =
block=20
enclosed with braces. So if the <SPAN class=3Dsmallcode>list</SPAN> had =
value=20
<SPAN class=3Dsmallcode>1,2</SPAN>, the above line would generate the =
line=20
containing <SPAN class=3Dsmallcode>foo&nbsp;1,2</SPAN>, which would then =
go=20
through the standard preprocessing. </P>
<P class=3Dsmalltext>The other special case is in the parameters of =
<SPAN=20
class=3Dsmallcode>rept</SPAN> directive. The amount of repetitions and =
the base=20
value for counter can be specified using numerical expressions, and if =
there is=20
a symbolic constant with non-numerical name used in such an expression,=20
preprocessor tries to evaluate its value as a numerical expression and =
if=20
succeeds, it replaces the symbolic constant with the result of that =
calculation=20
and continues to evaluate the primary expression. If the expression =
inside that=20
symbolic constants also contains some symbolic constants, preprocessor =
will try=20
to calculate all the needed values recursively. </P>
<P class=3Dsmalltext>This allows to perform some calculations at the =
time of=20
preprocessing, as long as all the values used are the numbers known at =
the=20
preprocessing stage. A single repetition with <SPAN =
class=3Dsmallcode>rept</SPAN>=20
can be used for the sole purpose of calculating some value, like in this =

example: </P><PRE class=3Dsmallcode>    define a b+4
    define b 3
    rept 1 result:a*b+2 { define c result }
</PRE>
<P class=3Dsmalltext>To compute the base value for <SPAN=20
class=3Dsmallcode>result</SPAN> counter, preprocessor replaces the <SPAN =

class=3Dsmallcode>b</SPAN> with its value and recursively calculates the =
value of=20
<SPAN class=3Dsmallcode>a</SPAN>, obtaining 7 as the result, then it =
calculates=20
the main expression with the result being 23. The <SPAN =
class=3Dsmallcode>c</SPAN>=20
then gets defined with the first value of counter (because the block is=20
processed just one time), which is the result of the computation, so the =
value=20
of <SPAN class=3Dsmallcode>c</SPAN> is simple <SPAN =
class=3Dsmallcode>23</SPAN>=20
symbol. Note that if <SPAN class=3Dsmallcode>b</SPAN> is later redefined =
with some=20
other numerical value, the next time and expression containing <SPAN=20
class=3Dsmallcode>a</SPAN> is calculated, the value of <SPAN=20
class=3Dsmallcode>a</SPAN> will reflect the new value of <SPAN=20
class=3Dsmallcode>b</SPAN>, because the symbolic constant contains just =
the text=20
of the expression. </P>
<P class=3Dsmalltext>There is one more special case - when preprocessor =
goes to=20
checking the second symbol in the line and it happens to be the colon =
character=20
(what is then interpreted by assembler as definition of a label), it =
stops in=20
this place and finishes the preprocessing of the first symbol (so if =
it's the=20
symbolic constant it gets unrolled) and if it still appears to be the =
label, it=20
performs the standard preprocessing starting from the place after the =
label.=20
This allows to place preprocessor directives and macroinstructions after =
the=20
labels, analogously to the instructions and directives processed by =
assembler,=20
like: </P><PRE class=3Dsmallcode>    start: include 'start.inc'
</PRE>
<P class=3Dsmalltext>However if the label becomes broken during =
preprocessing (for=20
example when it is the symbolic constant with empty value), only =
replacing of=20
the symbolic constants is continued for the rest of line. </P>
<P class=3Dsmalltext>It should be remembered, that the jobs performed by =

preprocessor are the preliminary operations on the texts symbols, that =
are done=20
in a simple single pass before the main process of assembly. The text =
that is=20
the result of preprocessing is passed to assembler, and it then does its =

multiple passes on it. Thus the control directives, which are recognized =
and=20
processed only by the assembler - as they are dependent on the numerical =
values=20
that may even vary between passes - are not recognized in any way by the =

preprocessor and have no effect on the preprocessing. Consider this =
example=20
source: </P><PRE class=3Dsmallcode>    if 0
    a =3D 1
    b equ 2
    end if
    dd b
</PRE>
<P class=3Dsmalltext>When it is preprocessed, they only directive that =
is=20
recognized by the preprocessor is the <SPAN =
class=3Dsmallcode>equ</SPAN>, which=20
defines symbolic constant <SPAN class=3Dsmallcode>b</SPAN>, so later in =
the source=20
the <SPAN class=3Dsmallcode>b</SPAN> symbol is replaced with the value =
<SPAN=20
class=3Dsmallcode>2</SPAN>. Except for this replacement, the other lines =
are=20
passes unchanged to the assembler. So after preprocessing the above =
source=20
becomes: </P><PRE class=3Dsmallcode>    if 0
    a =3D 1
    end if
    dd 2
</PRE>
<P class=3Dsmalltext>Now when assembler processes it, the condition for =
the <SPAN=20
class=3Dsmallcode>if</SPAN> is false, and the <SPAN =
class=3Dsmallcode>a</SPAN>=20
constant doesn't get defined. However symbolic constant <SPAN=20
class=3Dsmallcode>b</SPAN> was processed normally, even though its =
definition was=20
put just next to the one of <SPAN class=3Dsmallcode>a</SPAN>. So because =
of the=20
possible confusion you should be very careful every time when mixing the =

features of preprocessor and assembler - in such cases it is important =
to=20
realize what the source will become after the preprocessing, and thus =
what the=20
assembler will see and do its multiple passes on. </P>
<P><B><A class=3Dmediumtext name=3D2.4>2.4 Formatter directives</A> =
</B></P>
<P class=3Dsmalltext>These directives are actually also a kind of =
control=20
directives, with the purpose of controlling the format of generated =
code. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>format</SPAN> directive =
followed by the=20
format identifier allows to select the output format. This directive =
should be=20
put at the beginning of the source. Default output format is a flat =
binary file,=20
it can also be selected by using <SPAN class=3Dsmallcode>format =
binary</SPAN>=20
directive. This directive can be followed by the <SPAN =
class=3Dsmallcode>as</SPAN>=20
keyword and the quoted string specifying the default file extension for =
the=20
output file. Unless the output file name was specified from the command =
line,=20
assembler will use this extension when generating the output file. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>use16</SPAN> and <SPAN=20
class=3Dsmallcode>use32</SPAN> directives force the assembler to =
generate 16-bit=20
or 32-bit code, omitting the default setting for selected output format. =
<SPAN=20
class=3Dsmallcode>use64</SPAN> enables generating the code for the long =
mode of=20
x86-64 processors. </P>
<P class=3Dsmalltext>Below are described different output formats with =
the=20
directives specific to these formats. </P>
<P><B><A class=3Dsmalltext name=3D2.4.1>2.4.1 MZ executable</A> </B></P>
<P class=3Dsmalltext>To select the MZ output format, use <SPAN=20
class=3Dsmallcode>format MZ</SPAN> directive. The default code setting =
for this=20
format is 16-bit. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>segment</SPAN> directive =
defines a new=20
segment, it should be followed by label, which value will be the number =
of=20
defined segment, optionally <SPAN class=3Dsmallcode>use16</SPAN> or =
<SPAN=20
class=3Dsmallcode>use32</SPAN> word can follow to specify whether code =
in this=20
segment should be 16-bit or 32-bit. The origin of segment is aligned to=20
paragraph (16 bytes). All the labels defined then will have values =
relative to=20
the beginning of this segment. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>entry</SPAN> directive sets =
the entry=20
point for MZ executable, it should be followed by the far address (name =
of=20
segment, colon and the offset inside segment) of desired entry point. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>stack</SPAN> directive sets =
up the=20
stack for MZ executable. It can be followed by numerical expression =
specifying=20
the size of stack to be created automatically or by the far address of =
initial=20
stack frame when you want to set up the stack manually. When no stack is =

defined, the stack of default size 4096 bytes will be created. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>heap</SPAN> directive =
should be=20
followed by a 16-bit value defining maximum size of additional heap in=20
paragraphs (this is heap in addition to stack and undefined data). Use =
<SPAN=20
class=3Dsmallcode>heap 0</SPAN> to always allocate only memory program =
really=20
needs. Default size of heap is 65535. </P>
<P><B><A class=3Dsmalltext name=3D2.4.2>2.4.2 Portable Executable</A> =
</B></P>
<P class=3Dsmalltext>To select the Portable Executable output format, =
use <SPAN=20
class=3Dsmallcode>format PE</SPAN> directive, it can be followed by =
additional=20
format settings: first the target subsystem setting, which can be <SPAN=20
class=3Dsmallcode>console</SPAN> or <SPAN class=3Dsmallcode>GUI</SPAN> =
for Windows=20
applications, <SPAN class=3Dsmallcode>native</SPAN> for Windows drivers, =
<SPAN=20
class=3Dsmallcode>EFI</SPAN>, <SPAN class=3Dsmallcode>EFIboot</SPAN> or =
<SPAN=20
class=3Dsmallcode>EFIruntime</SPAN> for the UEFI, it may be followed by =
the=20
minimum version of system that the executable is targeted to (specified =
in form=20
of floating-point value). Optional <SPAN class=3Dsmallcode>DLL</SPAN> =
and <SPAN=20
class=3Dsmallcode>WDM</SPAN> keywords mark the output file as a dynamic =
link=20
library and WDM driver respectively, and the <SPAN =
class=3Dsmallcode>large</SPAN>=20
keyword marks the executable as able to handle addresses larger than 2 =
GB. </P>
<P class=3Dsmalltext>After those settings can follow the <SPAN=20
class=3Dsmallcode>at</SPAN> operator and the numerical expression =
specifying the=20
base of PE image and then optionally <SPAN class=3Dsmallcode>on</SPAN> =
operator=20
followed by the quoted string containing file name selects custom MZ =
stub for PE=20
program (when specified file is not a MZ executable, it is treated as a =
flat=20
binary executable file and converted into MZ format). The default code =
setting=20
for this format is 32-bit. The example of fully featured PE format =
declaration:=20
</P><PRE class=3Dsmallcode>    format PE GUI 4.0 DLL at 7000000h on =
'stub.exe'
</PRE>
<P class=3Dsmalltext>To create PE file for the x86-64 architecture, use =
<SPAN=20
class=3Dsmallcode>PE64</SPAN> keyword instead of <SPAN =
class=3Dsmallcode>PE</SPAN>=20
in the format declaration, in such case the long mode code is generated =
by=20
default. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>section</SPAN> directive =
defines a new=20
section, it should be followed by quoted string defining the name of =
section,=20
then one or more section flags can follow. Available flags are: <SPAN=20
class=3Dsmallcode>code</SPAN>, <SPAN class=3Dsmallcode>data</SPAN>, =
<SPAN=20
class=3Dsmallcode>readable</SPAN>, <SPAN =
class=3Dsmallcode>writeable</SPAN>, <SPAN=20
class=3Dsmallcode>executable</SPAN>, <SPAN =
class=3Dsmallcode>shareable</SPAN>, <SPAN=20
class=3Dsmallcode>discardable</SPAN>, <SPAN =
class=3Dsmallcode>notpageable</SPAN>.=20
The origin of section is aligned to page (4096 bytes). Example =
declaration of PE=20
section: </P><PRE class=3Dsmallcode>    section '.text' code readable =
executable
</PRE>
<P class=3Dsmalltext>Among with flags also one of the special PE data =
identifiers=20
can be specified to mark the whole section as a special data, possible=20
identifiers are <SPAN class=3Dsmallcode>export</SPAN>, <SPAN=20
class=3Dsmallcode>import</SPAN>, <SPAN class=3Dsmallcode>resource</SPAN> =
and <SPAN=20
class=3Dsmallcode>fixups</SPAN>. If the section is marked to contain =
fixups, they=20
are generated automatically and no more data needs to be defined in this =

section. Also resource data can be generated automatically from the =
resource=20
file, it can be achieved by writing the <SPAN =
class=3Dsmallcode>from</SPAN>=20
operator and quoted file name after the <SPAN =
class=3Dsmallcode>resource</SPAN>=20
identifier. Below are the examples of sections containing some special =
PE data:=20
</P><PRE class=3Dsmallcode>    section '.reloc' data readable =
discardable fixups
    section '.rsrc' data readable resource from 'my.res'
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>entry</SPAN> directive sets =
the entry=20
point for Portable Executable, the value of entry point should follow. =
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>stack</SPAN> directive sets =
up the size=20
of stack for Portable Executable, value of stack reserve size should =
follow,=20
optionally value of stack commit separated with comma can follow. When =
stack is=20
not defined, it's set by default to size of 4096 bytes. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>heap</SPAN> directive =
chooses the size=20
of heap for Portable Executable, value of heap reserve size should =
follow,=20
optionally value of heap commit separated with comma can follow. When no =
heap is=20
defined, it is set by default to size of 65536 bytes, when size of heap =
commit=20
is unspecified, it is by default set to zero. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>data</SPAN> directive =
begins the=20
definition of special PE data, it should be followed by one of the data=20
identifiers (<SPAN class=3Dsmallcode>export</SPAN>, <SPAN=20
class=3Dsmallcode>import</SPAN>, <SPAN class=3Dsmallcode>resource</SPAN> =
or <SPAN=20
class=3Dsmallcode>fixups</SPAN>) or by the number of data entry in PE =
header. The=20
data should be defined in next lines, ended with <SPAN =
class=3Dsmallcode>end=20
data</SPAN> directive. When fixups data definition is chosen, they are =
generated=20
automatically and no more data needs to be defined there. The same =
applies to=20
the resource data when the <SPAN class=3Dsmallcode>resource</SPAN> =
identifier is=20
followed by <SPAN class=3Dsmallcode>from</SPAN> operator and quoted file =
name - in=20
such case data is taken from the given resource file. </P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>rva</SPAN> operator can =
be used=20
inside the numerical expressions to obtain the RVA of the item addressed =
by the=20
value it is applied to, that is the offset relative to the base of PE =
image.=20
</P>
<P><B><A class=3Dsmalltext name=3D2.4.3>2.4.3 Common Object File =
Format</A> </B></P>
<P class=3Dsmalltext>To select Common Object File Format, use <SPAN=20
class=3Dsmallcode>format COFF</SPAN> or <SPAN class=3Dsmallcode>format =
MS=20
COFF</SPAN> directive, depending whether you want to create classic =
(DJGPP) or=20
Microsoft's variant of COFF file. The default code setting for this =
format is=20
32-bit. To create the file in Microsoft's COFF format for the x86-64=20
architecture, use <SPAN class=3Dsmallcode>format MS64 COFF</SPAN> =
setting, in such=20
case long mode code is generated by default. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>section</SPAN> directive =
defines a new=20
section, it should be followed by quoted string defining the name of =
section,=20
then one or more section flags can follow. Section flags available for =
both COFF=20
variants are <SPAN class=3Dsmallcode>code</SPAN> and <SPAN=20
class=3Dsmallcode>data</SPAN>, while flags <SPAN =
class=3Dsmallcode>readable</SPAN>,=20
<SPAN class=3Dsmallcode>writeable</SPAN>, <SPAN =
class=3Dsmallcode>executable</SPAN>,=20
<SPAN class=3Dsmallcode>shareable</SPAN>, <SPAN=20
class=3Dsmallcode>discardable</SPAN>, <SPAN =
class=3Dsmallcode>notpageable</SPAN>,=20
<SPAN class=3Dsmallcode>linkremove</SPAN> and <SPAN=20
class=3Dsmallcode>linkinfo</SPAN> are available only with Microsoft's =
COFF=20
variant. </P>
<P class=3Dsmalltext>By default section is aligned to double word (four =
bytes), in=20
case of Microsoft COFF variant other alignment can be specified by =
providing the=20
<SPAN class=3Dsmallcode>align</SPAN> operator followed by alignment =
value (any=20
power of two up to 8192) among the section flags. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>extrn</SPAN> directive =
defines the=20
external symbol, it should be followed by the name of symbol and =
optionally the=20
size operator specifying the size of data labeled by this symbol. The =
name of=20
symbol can be also preceded by quoted string containing name of the =
external=20
symbol and the <SPAN class=3Dsmallcode>as</SPAN> operator. Some example=20
declarations of external symbols: </P><PRE class=3Dsmallcode>    extrn =
exit
    extrn '__imp__MessageBoxA@16' as MessageBox:dword
</PRE>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>public</SPAN> directive =
declares the=20
existing symbol as public, it should be followed by the name of symbol,=20
optionally it can be followed by the <SPAN class=3Dsmallcode>as</SPAN> =
operator=20
and the quoted string containing name under which symbol should be =
available as=20
public. Some examples of public symbols declarations: </P><PRE =
class=3Dsmallcode>    public main
    public start as '_start'
</PRE>
<P class=3Dsmalltext>Additionally, with COFF format it's possible to =
specify=20
exported symbol as static, it's done by preceding the name of symbol =
with the=20
<SPAN class=3Dsmallcode>static</SPAN> keyword. </P>
<P class=3Dsmalltext>When using the Microsoft's COFF format, the <SPAN=20
class=3Dsmallcode>rva</SPAN> operator can be used inside the numerical =
expressions=20
to obtain the RVA of the item addressed by the value it is applied to. =
</P>
<P><B><A class=3Dsmalltext name=3D2.4.4>2.4.4 Executable and Linkable =
Format</A>=20
</B></P>
<P class=3Dsmalltext>To select ELF output format, use <SPAN =
class=3Dsmallcode>format=20
ELF</SPAN> directive. The default code setting for this format is =
32-bit. To=20
create ELF file for the x86-64 architecture, use <SPAN =
class=3Dsmallcode>format=20
ELF64</SPAN> directive, in such case the long mode code is generated by =
default.=20
</P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>section</SPAN> directive =
defines a new=20
section, it should be followed by quoted string defining the name of =
section,=20
then can follow one or both of the <SPAN =
class=3Dsmallcode>executable</SPAN> and=20
<SPAN class=3Dsmallcode>writeable</SPAN> flags, optionally also <SPAN=20
class=3Dsmallcode>align</SPAN> operator followed by the number =
specifying the=20
alignment of section (it has to be the power of two), if no alignment is =

specified, the default value is used, which is 4 or 8, depending on =
which format=20
variant has been chosen. </P>
<P class=3Dsmalltext><SPAN class=3Dsmallcode>extrn</SPAN> and <SPAN=20
class=3Dsmallcode>public</SPAN> directives have the same meaning and =
syntax as=20
when the COFF output format is selected (described in previous section). =
</P>
<P class=3Dsmalltext>The <SPAN class=3Dsmallcode>rva</SPAN> operator can =
be used=20
also in the case of this format (however not when target architecture is =

x86-64), it converts the address into the offset relative to the GOT =
table, so=20
it may be useful to create position-independent code. There's also a =
special=20
<SPAN class=3Dsmallcode>plt</SPAN> operator, which allows to call the =
external=20
functions through the Procedure Linkage Table. You can even create an =
alias for=20
external function that will make it always be called through PLT, with =
the code=20
like: </P><PRE class=3Dsmallcode>    extrn 'printf' as _printf
    printf =3D PLT _printf
</PRE>
<P class=3Dsmalltext>To create executable file, follow the format choice =
directive=20
with the <SPAN class=3Dsmallcode>executable</SPAN> keyword and =
optionally the=20
number specifying the brand of the target operating system (for example =
value 3=20
would mark the executable for Linux systems). With this format selected =
it is=20
allowed to use <SPAN class=3Dsmallcode>entry</SPAN> directive followed =
by the=20
value to set as entry point of program. On the other hand it makes <SPAN =

class=3Dsmallcode>extrn</SPAN> and <SPAN class=3Dsmallcode>public</SPAN> =
directives=20
unavailable, and instead of <SPAN class=3Dsmallcode>section</SPAN> there =
should be=20
the <SPAN class=3Dsmallcode>segment</SPAN> directive used, followed by =
one or more=20
segment permission flags and optionally a marker of special ELF =
executable=20
segment, which can be <SPAN class=3Dsmallcode>interpreter</SPAN>, <SPAN=20
class=3Dsmallcode>dynamic</SPAN> or <SPAN class=3Dsmallcode>note</SPAN>. =
The origin=20
of segment is aligned to page (4096 bytes), and available permission =
flags are:=20
<SPAN class=3Dsmallcode>readable</SPAN>, <SPAN =
class=3Dsmallcode>writeable</SPAN>=20
and <SPAN class=3Dsmallcode>executable</SPAN>. </P></DIV>
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